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1990-03-12
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Motorola 68000 Family Assembler (1.0 ) Mon Mar 12 15:32:21 1990
abs. rel. LC obj. code source line
---- ---- ---- --------- -----------
1 1 0000 |* $RCSfile: sim.sa $
2 2 0000 |* $Revision: 1.1 $
3 3 0000 |* $Date: 90/03/12 13:47:12 $
4 4 0000 |*
5 5 FFFF F000 |REG$ EQU $FFFFF000
6 6 0000 | INCLUDE "DEF.MAC"
7 1i 0000 |
8 2i 0000 |****************************************************************************
9 3i 0000 |* $RCSfile: def.mac $
10 4i 0000 |* $Revision: 1.1 $
11 5i 0000 |* $Date: 90/03/12 13:46:02 $
12 6i 0000 |*
13 7i 0000 |* -------------------------------------------------------------
14 8i 0000 |* Module Name: DEF - Define Symbols Macro
15 9i 0000 |* -------------------------------------------------------------
16 10i 0000 |*
17 11i 0000 |* Description:
18 12i 0000 |* 1. This file contains EQUates and a DEF macro for use with
19 13i 0000 |* MCU's that have internal registers and the bits in those
20 14i 0000 |* registers. By INCLUDE'ing this file with the specific MCU
21 15i 0000 |* equate file(s), mnemonic symbols are defined for the
22 16i 0000 |* internal registers and bits.
23 17i 0000 |* 2. The DEF macro controls how these mnemonic symbols are
24 18i 0000 |* defined. By channeling all symbol definitions through the
25 19i 0000 |* DEF macro, changes made to the DEF macro will affect ALL
26 20i 0000 |* symbol definitions upon re-assembly! See the DEF macro for
27 21i 0000 |* more details.
28 22i 0000 |*
29 23i 0000 |* Notes:
30 24i 0000 |* 1. Motorola reserves the right to make changes to this file.
31 25i 0000 |* Although this file has been carefully reviewed and is
32 26i 0000 |* believed to be reliable, Motorola does not assume any
33 27i 0000 |* liability arising out of its use. This code may be freely
34 28i 0000 |* used and/or modified at no cost or obligation to the user.
35 29i 0000 |* 2. All descriptions are WORD values unless stated otherwise.
36 30i 0000 |* 3. This file was made for use with the Motorola Development
37 31i 0000 |* Systems M68000 Family Structured Assembler for MS-DOS,
38 32i 0000 |* known as M68MASM.
39 33i 0000 |* 4. To use this file, either use an INCLUDE statement or just
40 34i 0000 |* merge this file and the appropriate MCU register equate
41 35i 0000 |* file(s) into your source code file. Consult your assem-
42 36i 0000 |* bler's user's manual for the details specific to your
43 37i 0000 |* situation.
44 38i 0000 |* 5. The latest version of this file is maintained on the
45 39i 0000 |* Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-
46 40i 0000 |* 3733). It operates continuously (except for maintenance)
47 41i 0000 |* at 1200-2400 baud, 8-bits, no parity. Download the
48 42i 0000 |* archive file <mcu>EQU.ARC to get all the files, where
49 43i 0000 |* <mcu> represents the processor type desired, i.e.
50 44i 0000 |* 332EQU.ARC for MC68332, etc.
51 45i 0000 |*
52 46i 0000 |****************************************************************************
53 47i 0000 |
54 48i 0000 |
55 49i 0000 |* Defines for Bit Definition Types (see DEF macro):
56 50i 0000 |*
57 51i 0000 0001 |BIT$NUM EQU 1 Bit numbers (0-15)
58 52i 0000 0002 |BIT$VAL EQU 2 Bit position values ($0000-$8000)
59 53i 0000 0003 |BIT$BOTH EQU BIT$NUM+BIT$VAL Both bit numbers and values
60 54i 0000 |*
61 55i 0000 0003 |BIT$CODE EQU BIT$BOTH Bit definitions for this assembly!
62 56i 0000 |* NOTE: Change BIT$CODE above to control bit definition types!
63 57i 0000 |
64 58i 0000 |
65 59i 0000 |* Bit Number Equates
66 60i 0000 |*
67 61i 0000 000F |.B15 EQU 15
68 62i 0000 000E |.B14 EQU 14
69 63i 0000 000D |.B13 EQU 13
70 64i 0000 000C |.B12 EQU 12
71 65i 0000 000B |.B11 EQU 11
72 66i 0000 000A |.B10 EQU 10
73 67i 0000 0009 |.B9 EQU 9
74 68i 0000 0008 |.B8 EQU 8
75 69i 0000 0007 |.B7 EQU 7
76 70i 0000 0006 |.B6 EQU 6
77 71i 0000 0005 |.B5 EQU 5
78 72i 0000 0004 |.B4 EQU 4
79 73i 0000 0003 |.B3 EQU 3
80 74i 0000 0002 |.B2 EQU 2
81 75i 0000 0001 |.B1 EQU 1
82 76i 0000 0000 |.B0 EQU 0
83 77i 0000 |
84 78i 0000 |
85 79i 0000 |* Bit Value Equates
86 80i 0000 |*
87 81i 0000 8000 |_B15 EQU 1<<.B15
88 82i 0000 4000 |_B14 EQU 1<<.B14
89 83i 0000 2000 |_B13 EQU 1<<.B13
90 84i 0000 1000 |_B12 EQU 1<<.B12
91 85i 0000 0800 |_B11 EQU 1<<.B11
92 86i 0000 0400 |_B10 EQU 1<<.B10
93 87i 0000 0200 |_B9 EQU 1<<.B9
94 88i 0000 0100 |_B8 EQU 1<<.B8
95 89i 0000 0080 |_B7 EQU 1<<.B7
96 90i 0000 0040 |_B6 EQU 1<<.B6
97 91i 0000 0020 |_B5 EQU 1<<.B5
98 92i 0000 0010 |_B4 EQU 1<<.B4
99 93i 0000 0008 |_B3 EQU 1<<.B3
100 94i 0000 0004 |_B2 EQU 1<<.B2
101 95i 0000 0002 |_B1 EQU 1<<.B1
102 96i 0000 0001 |_B0 EQU 1<<.B0
103 97i 0000 |
104 98i 0000 |
105 99i 0000 |* Mask Value Equates
106 100i 0000 |*
107 101i 0000 FFFF |MSK16 EQU $FFFF 16-bit mask
108 102i 0000 7FFF |MSK15 EQU $7FFF 15-bit mask
109 103i 0000 3FFF |MSK14 EQU $3FFF 14-bit mask
110 104i 0000 1FFF |MSK13 EQU $1FFF 13-bit mask
111 105i 0000 0FFF |MSK12 EQU $0FFF 12-bit mask
112 106i 0000 07FF |MSK11 EQU $07FF 11-bit mask
113 107i 0000 03FF |MSK10 EQU $03FF 10-bit mask
114 108i 0000 01FF |MSK9 EQU $01FF 9-bit mask
115 109i 0000 00FF |MSK8 EQU $00FF 8-bit mask
116 110i 0000 007F |MSK7 EQU $007F 7-bit mask
117 111i 0000 003F |MSK6 EQU $003F 6-bit mask
118 112i 0000 001F |MSK5 EQU $001F 5-bit mask
119 113i 0000 000F |MSK4 EQU $000F 4-bit mask
120 114i 0000 0007 |MSK3 EQU $0007 3-bit mask
121 115i 0000 0003 |MSK2 EQU $0003 2-bit mask
122 116i 0000 0001 |MSK1 EQU $0001 1-bit mask
123 117i 0000 |
124 118i 0000 |
125 119i 0000 |****************************************************************************
126 120i 0000 |* Define Bit Macro:
127 121i 0000 |* Syntax: DEF <name>,<value>[,<field size>[,<reg size>]]
128 122i 0000 |*
129 123i 0000 |* where: <name> is the bit name to be defined.
130 124i 0000 |* <value> is the bit number associated with <name>;
131 125i 0000 |* must be entered as "Bn", where "n" = 0-15.
132 126i 0000 |* <field size> is the optional bit field size starting with
133 127i 0000 |* <value> which must be the least significant
134 128i 0000 |* bit (LSB) of the field. When this parameter
135 129i 0000 |* is present, only the bit field and bit number
136 130i 0000 |* labels are defined.
137 131i 0000 |* <reg size> is the optional size of the register, entered
138 132i 0000 |* as "MSK8" for BYTE sized operands (8-bit).
139 133i 0000 |* The default value is "MSK16" for WORD sized
140 134i 0000 |* operands.
141 135i 0000 |* Action:
142 136i 0000 |* Defines bit number, bit value, or bit field labels based on the
143 137i 0000 |* <name> label and the value of BIT$CODE (defined above).
144 138i 0000 |* Label Key:
145 139i 0000 |* Period prefix (.) denotes bit number label.
146 140i 0000 |* Underscore prefix (_) denotes bit value label.
147 141i 0000 |* Underscore suffix (_) denotes bit field label.
148 142i 0000 |* Underscore MSK suffix (_MSK) denotes bit field mask label.
149 143i 0000 |* Underscore NMSK suffix (_NMSK) denotes not-bit field mask label.
150 144i 0000 |* Label Examples:
151 145i 0000 |* .NAME = bit number label, i.e. 0-15
152 146i 0000 |* _NAME = bit value label, i.e. $0000-$8000
153 147i 0000 |* NAME_ = bit field value label, i.e. $0100 (LSB of field)
154 148i 0000 |* NAME_MSK = bit field mask label, i.e. $0700 (3-bit field)
155 149i 0000 |* NAME_NMSK = bit field not-mask label, i.e. $F8FF (3-bit field)
156 150i 0000 |*
157 151i 0000 |* Notes:
158 152i 0000 |* 1. The "SET" directive is used here instead of the "EQU" directive
159 153i 0000 |* to allow multiple definitions of the same bit labels that are
160 154i 0000 |* used for multiple registers, each with the same values.
161 155i 0000 |* 2. If the user changes the predefined label rules per the Label Key
162 156i 0000 |* above, it is their responsibility to ensure duplicate labels with
163 157i 0000 |* different bit values do not occur!
164 158i 0000 |*
165 159i 0000 |DEF MACRO
166 160i 0000 | IFC "","\3"
167 161i 0000 | IFNE BIT$CODE&BIT$NUM
168 162i 0000 |.\1 SET .\2
169 163i 0000 | ENDC
170 164i 0000 | IFNE BIT$CODE&BIT$VAL
171 165i 0000 |_\1 SET _\2
172 166i 0000 | ENDC
173 167i 0000 | ENDC
174 168i 0000 | IFNC "","\3"
175 169i 0000 |.\1 SET .\2
176 170i 0000 |\1_ SET _\2
177 171i 0000 |\1_MSK SET (MSK\3)<<.\2
178 172i 0000 | IFC "","\4"
179 173i 0000 |\1_NMSK SET (-\1_MSK-1)&MSK16
180 174i 0000 | ENDC
181 175i 0000 | IFNC "","\4"
182 176i 0000 |\1_NMSK SET (-\1_MSK-1)&\4
183 177i 0000 | ENDC
184 178i 0000 | ENDC
185 179i 0000 | ENDM
186 180i 0000 |
187 181i 0000 0000 | IFNE 0 ------- don't assemble unless needed --------
188 182i 0000 | DEF NBL0,B0,4 . nibble 0
189 183i 0000 | DEF NBL1,B4,4 . nibble 1
190 184i 0000 | DEF NBL2,B8,4 . nibble 2
191 185i 0000 | DEF NBL3,B12,4 . nibble 3
192 186i 0000 |
193 187i 0000 | DEF HNBL0,B0,2 . half nibble 0
194 188i 0000 | DEF HNBL1,B2,2 . half nibble 1
195 189i 0000 | DEF HNBL2,B4,2 . half nibble 2
196 190i 0000 | DEF HNBL3,B6,2 . half nibble 3
197 191i 0000 | DEF HNBL4,B8,2 . half nibble 4
198 192i 0000 | DEF HNBL5,B10,2 . half nibble 5
199 193i 0000 | DEF HNBL6,B12,2 . half nibble 6
200 194i 0000 | DEF HNBL7,B14,2 . half nibble 7
201 195i 0000 | ENDC
202 7 0000 | INCLUDE "332SIM.EQU"
203 1i 0000 |
204 2i 0000 |****************************************************************************
205 3i 0000 |* $RCSfile: 332sim.equ $
206 4i 0000 |* $Revision: 1.1 $
207 5i 0000 |* $Date: 90/03/12 13:45:42 $
208 6i 0000 |*
209 7i 0000 |* -------------------------------------------------------------
210 8i 0000 |* Module Name: 332SIM - MC68332 SIM Registers
211 9i 0000 |* -------------------------------------------------------------
212 10i 0000 |*
213 11i 0000 |* Description:
214 12i 0000 |* 1. This file contains EQUates for all the System Integration
215 13i 0000 |* Module (SIM) registers and bits for the MC68332. Consult
216 14i 0000 |* the "MC68332 System Integration Module User's Manual", part
217 15i 0000 |* number SIM32UM/AD, for more details.
218 16i 0000 |* 2. A 128-byte address space is reserved for the SIM, though not
219 17i 0000 |* all are used.
220 18i 0000 |* 3. The ABSOLUTE address area where the register array block
221 19i 0000 |* appears in memory is specified by the value of REG$, which
222 20i 0000 |* should be defined in the user's system definitions. The
223 21i 0000 |* value of REG$ is $YFF000, where Y = M111 and M reflects the
224 22i 0000 |* modmap bit (MM) in the module configuration register (MCR).
225 23i 0000 |*
226 24i 0000 |* REG$ value Comments
227 25i 0000 |* ---------- ---------------------------------
228 26i 0000 |* $007FF000 MCR MM bit = 0
229 27i 0000 |* $00FFF000 MCR MM bit = 1 (reset default)
230 28i 0000 |* $FFFFF000 MCR MM bit = 1 (reset default)
231 29i 0000 |* Forces short addressing (unused
232 30i 0000 |* upper address lines are ignored)
233 31i 0000 |* 4. The following pages summarize these registers and their
234 32i 0000 |* associated addresses.
235 33i 0000 |*
236 34i 0000 |* Notes:
237 35i 0000 |* 1. Motorola reserves the right to make changes to this file.
238 36i 0000 |* Although this file has been carefully reviewed and is
239 37i 0000 |* believed to be reliable, Motorola does not assume any
240 38i 0000 |* liability arising out of its use. This code may be freely
241 39i 0000 |* used and/or modified at no cost or obligation to the user.
242 40i 0000 |* 2. All descriptions are WORD values unless stated otherwise.
243 41i 0000 |* 3. The DEF macro along with the BIT$CODE symbol controls the
244 42i 0000 |* actual bit definitions. See the DEF macro in the DEF.MAC
245 43i 0000 |* file for details.
246 44i 0000 |* 4. This file was made for use with the Motorola Development
247 45i 0000 |* Systems M68000 Family Structured Assembler for MS-DOS,
248 46i 0000 |* known as M68MASM.
249 47i 0000 |* 5. To use this file, either use an INCLUDE statement or just
250 48i 0000 |* merge this file into your source code file. Consult your
251 49i 0000 |* assembler's user's manual for the details specific to your
252 50i 0000 |* situation. Reference the code segment example below for
253 51i 0000 |* usage ideas (shown in M68MASM for MS-DOS syntax).
254 52i 0000 |*
255 53i 0000 |* REG$ EQU $FFFFF000 Register base address
256 54i 0000 |* * NOTE: A31-24 unused in MC68332, so we set them all =1
257 55i 0000 |* * in order to use absolute short addressing mode!
258 56i 0000 |* NOLIST
259 57i 0000 |* INCLUDE "DEF.MAC"
260 58i 0000 |* INCLUDE "332SIM.EQU"
261 59i 0000 |* LIST
262 60i 0000 |* START CLR SIM$+SIMTR Absolute addressing!
263 61i 0000 |* LEA SIM$,A6 . OR
264 62i 0000 |* CLR (SIMTR,A6) Indexed addressing!
265 63i 0000 |* * Bit number usage w/indexing!
266 64i 0000 |* BCLR.B #MM,(MCR+1,A6)
267 65i 0000 |* OR.W (1<<.FRZBM)+(1<<.FRZSW),(MCR,A6)
268 66i 0000 |* * Bit value usage w/indexing!
269 67i 0000 |* AND.B #(-_MM-1)&$FF,(MCR+1,A6)
270 68i 0000 |* OR.W _FRZBM+_FRZSW,(MCR,A6)
271 69i 0000 |* * Bit field usage w/indexing!
272 70i 0000 |* MOVE.B #(5*PIRQL_)+(66*PIV_),(PICR,A6)
273 71i 0000 |* * Bit field mask usage w/indexing!
274 72i 0000 |* MOVE.W (PICR,A6),D0
275 73i 0000 |* MOVE.W D0,D1
276 74i 0000 |* AND.W #PIRQL_MSK,D0 Isolate PIRQL field
277 75i 0000 |* MOVE.L #.PIRQL,D2
278 76i 0000 |* LSR.W D2,d0 and right justify it!
279 77i 0000 |* AND.W #PIRQL_NMSK,D1 Clear PIRQL field.
280 78i 0000 |*
281 79i 0000 |* For bit fields, a value (0-N) will be placed inside. As
282 80i 0000 |* can be seen in the last line above, this is accomplished
283 81i 0000 |* by multiplying the bit field label by the desired value
284 82i 0000 |* for the field. This line initializes the PICR register
285 83i 0000 |* which has two bit fields, PIRQL_ and PIV_. These fields
286 84i 0000 |* are initialized to interrupt level 5 and vector 66
287 85i 0000 |* respectively, by this line (places a value of $0542 into
288 86i 0000 |* the PICR register).
289 87i 0000 |* 6. Be careful when using any of the BIT instructions (BCHG,
290 88i 0000 |* BCLR, BSET, BTST), as they will only operate on a BYTE of
291 89i 0000 |* memory, not a WORD. Thus to access a bit in the least
292 90i 0000 |* significant half of a word sized register (B0-B7), "+1"
293 91i 0000 |* must be added to the operand address. See the code
294 92i 0000 |* segment example in item 5 above.
295 93i 0000 |* 7. Because the equate files can generate many listing pages,
296 94i 0000 |* the user may wish to disable the listing via NOLIST and
297 95i 0000 |* LIST directives as seen in the above example code.
298 96i 0000 |* 8. The latest version of this file is maintained on the
299 97i 0000 |* Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-
300 98i 0000 |* 3733). It operates continuously (except for maintenance)
301 99i 0000 |* at 1200-2400 baud, 8-bits, no parity. Download the
302 100i 0000 |* archive file 332EQU.ARC to get all the files.
303 101i 0000 |*
304 102i 0000 |****************************************************************************
305 103i 0000 |
306 104i 0000 |
307 105i 0000 |*********************************************************************
308 106i 0000 |* Define Module Base Address
309 107i 0000 |*********************************************************************
310 108i FFFF FA00 |SIM$ EQU REG$+$A00 SIM base address
311 109i 0000 |
312 110i 0000 |*********************************************************************
313 111i 0000 |* Define Registers and Bits
314 112i 0000 |*********************************************************************
315 113i 0000 0000 |MCR EQU $000 Module Configuration Register
316 114i 0000 | DEF EXOFF,B15 . external clock off
317 1m 0000 + IFC "",""
318 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
319 3m 0000 000F +.EXOFF SET .B15
320 4m 0000 + ENDC
321 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
322 6m 0000 8000 +_EXOFF SET _B15
323 7m 0000 + ENDC
324 8m 0000 + ENDC
325 9m 0000 + IFNC "",""
326 10m 0000 +.EXOFF SET .B15
327 11m 0000 +EXOFF_ SET _B15
328 12m 0000 +EXOFF_MSK SET (MSK)<<.B15
329 13m 0000 + IFC "",""
330 14m 0000 +EXOFF_NMSK SET (-EXOFF_MSK-1)&MSK16
331 15m 0000 + ENDC
332 16m 0000 + IFNC "",""
333 17m 0000 +EXOFF_NMSK SET (-EXOFF_MSK-1)&
334 18m 0000 + ENDC
335 19m 0000 + ENDC
336 115i 0000 | DEF FRZSW,B14 . freeze software enable
337 1m 0000 + IFC "",""
338 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
339 3m 0000 000E +.FRZSW SET .B14
340 4m 0000 + ENDC
341 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
342 6m 0000 4000 +_FRZSW SET _B14
343 7m 0000 + ENDC
344 8m 0000 + ENDC
345 9m 0000 + IFNC "",""
346 10m 0000 +.FRZSW SET .B14
347 11m 0000 +FRZSW_ SET _B14
348 12m 0000 +FRZSW_MSK SET (MSK)<<.B14
349 13m 0000 + IFC "",""
350 14m 0000 +FRZSW_NMSK SET (-FRZSW_MSK-1)&MSK16
351 15m 0000 + ENDC
352 16m 0000 + IFNC "",""
353 17m 0000 +FRZSW_NMSK SET (-FRZSW_MSK-1)&
354 18m 0000 + ENDC
355 19m 0000 + ENDC
356 116i 0000 | DEF FRZBM,B13 . freeze bus monitor enable
357 1m 0000 + IFC "",""
358 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
359 3m 0000 000D +.FRZBM SET .B13
360 4m 0000 + ENDC
361 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
362 6m 0000 2000 +_FRZBM SET _B13
363 7m 0000 + ENDC
364 8m 0000 + ENDC
365 9m 0000 + IFNC "",""
366 10m 0000 +.FRZBM SET .B13
367 11m 0000 +FRZBM_ SET _B13
368 12m 0000 +FRZBM_MSK SET (MSK)<<.B13
369 13m 0000 + IFC "",""
370 14m 0000 +FRZBM_NMSK SET (-FRZBM_MSK-1)&MSK16
371 15m 0000 + ENDC
372 16m 0000 + IFNC "",""
373 17m 0000 +FRZBM_NMSK SET (-FRZBM_MSK-1)&
374 18m 0000 + ENDC
375 19m 0000 + ENDC
376 117i 0000 | DEF SLVEN,B11 . slave mode enable
377 1m 0000 + IFC "",""
378 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
379 3m 0000 000B +.SLVEN SET .B11
380 4m 0000 + ENDC
381 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
382 6m 0000 0800 +_SLVEN SET _B11
383 7m 0000 + ENDC
384 8m 0000 + ENDC
385 9m 0000 + IFNC "",""
386 10m 0000 +.SLVEN SET .B11
387 11m 0000 +SLVEN_ SET _B11
388 12m 0000 +SLVEN_MSK SET (MSK)<<.B11
389 13m 0000 + IFC "",""
390 14m 0000 +SLVEN_NMSK SET (-SLVEN_MSK-1)&MSK16
391 15m 0000 + ENDC
392 16m 0000 + IFNC "",""
393 17m 0000 +SLVEN_NMSK SET (-SLVEN_MSK-1)&
394 18m 0000 + ENDC
395 19m 0000 + ENDC
396 118i 0000 | DEF SHEN,B8,2 . show cycle enable (2 bits)
397 1m 0000 + IFC "","2"
398 2m 0000 + IFNE BIT$CODE&BIT$NUM
399 3m 0000 +.SHEN SET .B8
400 4m 0000 + ENDC
401 5m 0000 + IFNE BIT$CODE&BIT$VAL
402 6m 0000 +_SHEN SET _B8
403 7m 0000 + ENDC
404 8m 0000 + ENDC
405 9m 0000 + IFNC "","2"
406 10m 0000 0008 +.SHEN SET .B8
407 11m 0000 0100 +SHEN_ SET _B8
408 12m 0000 0300 +SHEN_MSK SET (MSK2)<<.B8
409 13m 0000 + IFC "",""
410 14m 0000 FCFF +SHEN_NMSK SET (-SHEN_MSK-1)&MSK16
411 15m 0000 + ENDC
412 16m 0000 + IFNC "",""
413 17m 0000 +SHEN_NMSK SET (-SHEN_MSK-1)&
414 18m 0000 + ENDC
415 19m 0000 + ENDC
416 119i 0000 | DEF SUPV,B7 . supervisor/unrestricted data space
417 1m 0000 + IFC "",""
418 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
419 3m 0000 0007 +.SUPV SET .B7
420 4m 0000 + ENDC
421 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
422 6m 0000 0080 +_SUPV SET _B7
423 7m 0000 + ENDC
424 8m 0000 + ENDC
425 9m 0000 + IFNC "",""
426 10m 0000 +.SUPV SET .B7
427 11m 0000 +SUPV_ SET _B7
428 12m 0000 +SUPV_MSK SET (MSK)<<.B7
429 13m 0000 + IFC "",""
430 14m 0000 +SUPV_NMSK SET (-SUPV_MSK-1)&MSK16
431 15m 0000 + ENDC
432 16m 0000 + IFNC "",""
433 17m 0000 +SUPV_NMSK SET (-SUPV_MSK-1)&
434 18m 0000 + ENDC
435 19m 0000 + ENDC
436 120i 0000 | DEF MM,B6 . module mapping
437 1m 0000 + IFC "",""
438 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
439 3m 0000 0006 +.MM SET .B6
440 4m 0000 + ENDC
441 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
442 6m 0000 0040 +_MM SET _B6
443 7m 0000 + ENDC
444 8m 0000 + ENDC
445 9m 0000 + IFNC "",""
446 10m 0000 +.MM SET .B6
447 11m 0000 +MM_ SET _B6
448 12m 0000 +MM_MSK SET (MSK)<<.B6
449 13m 0000 + IFC "",""
450 14m 0000 +MM_NMSK SET (-MM_MSK-1)&MSK16
451 15m 0000 + ENDC
452 16m 0000 + IFNC "",""
453 17m 0000 +MM_NMSK SET (-MM_MSK-1)&
454 18m 0000 + ENDC
455 19m 0000 + ENDC
456 121i 0000 |* NOTE: MM is a WRITE-ONCE field!
457 122i 0000 | DEF IARB,B0,4 . interrupt arbitration (4 bits)
458 1m 0000 + IFC "","4"
459 2m 0000 + IFNE BIT$CODE&BIT$NUM
460 3m 0000 +.IARB SET .B0
461 4m 0000 + ENDC
462 5m 0000 + IFNE BIT$CODE&BIT$VAL
463 6m 0000 +_IARB SET _B0
464 7m 0000 + ENDC
465 8m 0000 + ENDC
466 9m 0000 + IFNC "","4"
467 10m 0000 0000 +.IARB SET .B0
468 11m 0000 0001 +IARB_ SET _B0
469 12m 0000 000F +IARB_MSK SET (MSK4)<<.B0
470 13m 0000 + IFC "",""
471 14m 0000 FFF0 +IARB_NMSK SET (-IARB_MSK-1)&MSK16
472 15m 0000 + ENDC
473 16m 0000 + IFNC "",""
474 17m 0000 +IARB_NMSK SET (-IARB_MSK-1)&
475 18m 0000 + ENDC
476 19m 0000 + ENDC
477 123i 0000 |*-------------------------------------------------------------------*
478 124i 0000 0002 |SIMTR EQU $002 System Integration Module Test Register
479 125i 0000 | DEF MASK,B10,6 . mask number (read only) (6 bits)
480 1m 0000 + IFC "","6"
481 2m 0000 + IFNE BIT$CODE&BIT$NUM
482 3m 0000 +.MASK SET .B10
483 4m 0000 + ENDC
484 5m 0000 + IFNE BIT$CODE&BIT$VAL
485 6m 0000 +_MASK SET _B10
486 7m 0000 + ENDC
487 8m 0000 + ENDC
488 9m 0000 + IFNC "","6"
489 10m 0000 000A +.MASK SET .B10
490 11m 0000 0400 +MASK_ SET _B10
491 12m 0000 FC00 +MASK_MSK SET (MSK6)<<.B10
492 13m 0000 + IFC "",""
493 14m 0000 03FF +MASK_NMSK SET (-MASK_MSK-1)&MSK16
494 15m 0000 + ENDC
495 16m 0000 + IFNC "",""
496 17m 0000 +MASK_NMSK SET (-MASK_MSK-1)&
497 18m 0000 + ENDC
498 19m 0000 + ENDC
499 126i 0000 | DEF SOSEL,B6,2 . scan out select (2 bits)
500 1m 0000 + IFC "","2"
501 2m 0000 + IFNE BIT$CODE&BIT$NUM
502 3m 0000 +.SOSEL SET .B6
503 4m 0000 + ENDC
504 5m 0000 + IFNE BIT$CODE&BIT$VAL
505 6m 0000 +_SOSEL SET _B6
506 7m 0000 + ENDC
507 8m 0000 + ENDC
508 9m 0000 + IFNC "","2"
509 10m 0000 0006 +.SOSEL SET .B6
510 11m 0000 0040 +SOSEL_ SET _B6
511 12m 0000 00C0 +SOSEL_MSK SET (MSK2)<<.B6
512 13m 0000 + IFC "",""
513 14m 0000 FF3F +SOSEL_NMSK SET (-SOSEL_MSK-1)&MSK16
514 15m 0000 + ENDC
515 16m 0000 + IFNC "",""
516 17m 0000 +SOSEL_NMSK SET (-SOSEL_MSK-1)&
517 18m 0000 + ENDC
518 19m 0000 + ENDC
519 127i 0000 |* NOTE: SOSEL bit field is different bit position from TPU's TTCR!
520 128i 0000 | DEF SHIRQ,B4,2 . show interrupt request (2 bits)
521 1m 0000 + IFC "","2"
522 2m 0000 + IFNE BIT$CODE&BIT$NUM
523 3m 0000 +.SHIRQ SET .B4
524 4m 0000 + ENDC
525 5m 0000 + IFNE BIT$CODE&BIT$VAL
526 6m 0000 +_SHIRQ SET _B4
527 7m 0000 + ENDC
528 8m 0000 + ENDC
529 9m 0000 + IFNC "","2"
530 10m 0000 0004 +.SHIRQ SET .B4
531 11m 0000 0010 +SHIRQ_ SET _B4
532 12m 0000 0030 +SHIRQ_MSK SET (MSK2)<<.B4
533 13m 0000 + IFC "",""
534 14m 0000 FFCF +SHIRQ_NMSK SET (-SHIRQ_MSK-1)&MSK16
535 15m 0000 + ENDC
536 16m 0000 + IFNC "",""
537 17m 0000 +SHIRQ_NMSK SET (-SHIRQ_MSK-1)&
538 18m 0000 + ENDC
539 19m 0000 + ENDC
540 129i 0000 | DEF FBIT,B2,2 . force bit (2 bits)
541 1m 0000 + IFC "","2"
542 2m 0000 + IFNE BIT$CODE&BIT$NUM
543 3m 0000 +.FBIT SET .B2
544 4m 0000 + ENDC
545 5m 0000 + IFNE BIT$CODE&BIT$VAL
546 6m 0000 +_FBIT SET _B2
547 7m 0000 + ENDC
548 8m 0000 + ENDC
549 9m 0000 + IFNC "","2"
550 10m 0000 0002 +.FBIT SET .B2
551 11m 0000 0004 +FBIT_ SET _B2
552 12m 0000 000C +FBIT_MSK SET (MSK2)<<.B2
553 13m 0000 + IFC "",""
554 14m 0000 FFF3 +FBIT_NMSK SET (-FBIT_MSK-1)&MSK16
555 15m 0000 + ENDC
556 16m 0000 + IFNC "",""
557 17m 0000 +FBIT_NMSK SET (-FBIT_MSK-1)&
558 18m 0000 + ENDC
559 19m 0000 + ENDC
560 130i 0000 | DEF BWC,B0,2 . bandwidth control (2 bits)
561 1m 0000 + IFC "","2"
562 2m 0000 + IFNE BIT$CODE&BIT$NUM
563 3m 0000 +.BWC SET .B0
564 4m 0000 + ENDC
565 5m 0000 + IFNE BIT$CODE&BIT$VAL
566 6m 0000 +_BWC SET _B0
567 7m 0000 + ENDC
568 8m 0000 + ENDC
569 9m 0000 + IFNC "","2"
570 10m 0000 0000 +.BWC SET .B0
571 11m 0000 0001 +BWC_ SET _B0
572 12m 0000 0003 +BWC_MSK SET (MSK2)<<.B0
573 13m 0000 + IFC "",""
574 14m 0000 FFFC +BWC_NMSK SET (-BWC_MSK-1)&MSK16
575 15m 0000 + ENDC
576 16m 0000 + IFNC "",""
577 17m 0000 +BWC_NMSK SET (-BWC_MSK-1)&
578 18m 0000 + ENDC
579 19m 0000 + ENDC
580 131i 0000 |*-------------------------------------------------------------------*
581 132i 0000 0004 |SYNCR EQU $004 Clock Synthesizer Control Register
582 133i 0000 |* NOTE: M68MASM doesn't allow labels like ".W" and ".X"!
583 134i 0000 | DEF WBIT,B15 . W frequency control bit
584 1m 0000 + IFC "",""
585 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
586 3m 0000 000F +.WBIT SET .B15
587 4m 0000 + ENDC
588 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
589 6m 0000 8000 +_WBIT SET _B15
590 7m 0000 + ENDC
591 8m 0000 + ENDC
592 9m 0000 + IFNC "",""
593 10m 0000 +.WBIT SET .B15
594 11m 0000 +WBIT_ SET _B15
595 12m 0000 +WBIT_MSK SET (MSK)<<.B15
596 13m 0000 + IFC "",""
597 14m 0000 +WBIT_NMSK SET (-WBIT_MSK-1)&MSK16
598 15m 0000 + ENDC
599 16m 0000 + IFNC "",""
600 17m 0000 +WBIT_NMSK SET (-WBIT_MSK-1)&
601 18m 0000 + ENDC
602 19m 0000 + ENDC
603 135i 0000 | DEF XBIT,B14 . X frequency control bit
604 1m 0000 + IFC "",""
605 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
606 3m 0000 000E +.XBIT SET .B14
607 4m 0000 + ENDC
608 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
609 6m 0000 4000 +_XBIT SET _B14
610 7m 0000 + ENDC
611 8m 0000 + ENDC
612 9m 0000 + IFNC "",""
613 10m 0000 +.XBIT SET .B14
614 11m 0000 +XBIT_ SET _B14
615 12m 0000 +XBIT_MSK SET (MSK)<<.B14
616 13m 0000 + IFC "",""
617 14m 0000 +XBIT_NMSK SET (-XBIT_MSK-1)&MSK16
618 15m 0000 + ENDC
619 16m 0000 + IFNC "",""
620 17m 0000 +XBIT_NMSK SET (-XBIT_MSK-1)&
621 18m 0000 + ENDC
622 19m 0000 + ENDC
623 136i 0000 | DEF Y,B8,6 . Y frequency control bits (6 bits)
624 1m 0000 + IFC "","6"
625 2m 0000 + IFNE BIT$CODE&BIT$NUM
626 3m 0000 +.Y SET .B8
627 4m 0000 + ENDC
628 5m 0000 + IFNE BIT$CODE&BIT$VAL
629 6m 0000 +_Y SET _B8
630 7m 0000 + ENDC
631 8m 0000 + ENDC
632 9m 0000 + IFNC "","6"
633 10m 0000 0008 +.Y SET .B8
634 11m 0000 0100 +Y_ SET _B8
635 12m 0000 3F00 +Y_MSK SET (MSK6)<<.B8
636 13m 0000 + IFC "",""
637 14m 0000 C0FF +Y_NMSK SET (-Y_MSK-1)&MSK16
638 15m 0000 + ENDC
639 16m 0000 + IFNC "",""
640 17m 0000 +Y_NMSK SET (-Y_MSK-1)&
641 18m 0000 + ENDC
642 19m 0000 + ENDC
643 137i 0000 | DEF EDIV,B7 . E-clock divide rate
644 1m 0000 + IFC "",""
645 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
646 3m 0000 0007 +.EDIV SET .B7
647 4m 0000 + ENDC
648 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
649 6m 0000 0080 +_EDIV SET _B7
650 7m 0000 + ENDC
651 8m 0000 + ENDC
652 9m 0000 + IFNC "",""
653 10m 0000 +.EDIV SET .B7
654 11m 0000 +EDIV_ SET _B7
655 12m 0000 +EDIV_MSK SET (MSK)<<.B7
656 13m 0000 + IFC "",""
657 14m 0000 +EDIV_NMSK SET (-EDIV_MSK-1)&MSK16
658 15m 0000 + ENDC
659 16m 0000 + IFNC "",""
660 17m 0000 +EDIV_NMSK SET (-EDIV_MSK-1)&
661 18m 0000 + ENDC
662 19m 0000 + ENDC
663 138i 0000 | DEF SLIMP,B4 . limp mode
664 1m 0000 + IFC "",""
665 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
666 3m 0000 0004 +.SLIMP SET .B4
667 4m 0000 + ENDC
668 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
669 6m 0000 0010 +_SLIMP SET _B4
670 7m 0000 + ENDC
671 8m 0000 + ENDC
672 9m 0000 + IFNC "",""
673 10m 0000 +.SLIMP SET .B4
674 11m 0000 +SLIMP_ SET _B4
675 12m 0000 +SLIMP_MSK SET (MSK)<<.B4
676 13m 0000 + IFC "",""
677 14m 0000 +SLIMP_NMSK SET (-SLIMP_MSK-1)&MSK16
678 15m 0000 + ENDC
679 16m 0000 + IFNC "",""
680 17m 0000 +SLIMP_NMSK SET (-SLIMP_MSK-1)&
681 18m 0000 + ENDC
682 19m 0000 + ENDC
683 139i 0000 | DEF SLOCK,B3 . synthesizer lock
684 1m 0000 + IFC "",""
685 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
686 3m 0000 0003 +.SLOCK SET .B3
687 4m 0000 + ENDC
688 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
689 6m 0000 0008 +_SLOCK SET _B3
690 7m 0000 + ENDC
691 8m 0000 + ENDC
692 9m 0000 + IFNC "",""
693 10m 0000 +.SLOCK SET .B3
694 11m 0000 +SLOCK_ SET _B3
695 12m 0000 +SLOCK_MSK SET (MSK)<<.B3
696 13m 0000 + IFC "",""
697 14m 0000 +SLOCK_NMSK SET (-SLOCK_MSK-1)&MSK16
698 15m 0000 + ENDC
699 16m 0000 + IFNC "",""
700 17m 0000 +SLOCK_NMSK SET (-SLOCK_MSK-1)&
701 18m 0000 + ENDC
702 19m 0000 + ENDC
703 140i 0000 | DEF RSTEN,B2 . reset enable
704 1m 0000 + IFC "",""
705 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
706 3m 0000 0002 +.RSTEN SET .B2
707 4m 0000 + ENDC
708 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
709 6m 0000 0004 +_RSTEN SET _B2
710 7m 0000 + ENDC
711 8m 0000 + ENDC
712 9m 0000 + IFNC "",""
713 10m 0000 +.RSTEN SET .B2
714 11m 0000 +RSTEN_ SET _B2
715 12m 0000 +RSTEN_MSK SET (MSK)<<.B2
716 13m 0000 + IFC "",""
717 14m 0000 +RSTEN_NMSK SET (-RSTEN_MSK-1)&MSK16
718 15m 0000 + ENDC
719 16m 0000 + IFNC "",""
720 17m 0000 +RSTEN_NMSK SET (-RSTEN_MSK-1)&
721 18m 0000 + ENDC
722 19m 0000 + ENDC
723 141i 0000 | DEF STSIM,B1 . stop mode system integration clock
724 1m 0000 + IFC "",""
725 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
726 3m 0000 0001 +.STSIM SET .B1
727 4m 0000 + ENDC
728 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
729 6m 0000 0002 +_STSIM SET _B1
730 7m 0000 + ENDC
731 8m 0000 + ENDC
732 9m 0000 + IFNC "",""
733 10m 0000 +.STSIM SET .B1
734 11m 0000 +STSIM_ SET _B1
735 12m 0000 +STSIM_MSK SET (MSK)<<.B1
736 13m 0000 + IFC "",""
737 14m 0000 +STSIM_NMSK SET (-STSIM_MSK-1)&MSK16
738 15m 0000 + ENDC
739 16m 0000 + IFNC "",""
740 17m 0000 +STSIM_NMSK SET (-STSIM_MSK-1)&
741 18m 0000 + ENDC
742 19m 0000 + ENDC
743 142i 0000 | DEF STEXT,B0 . stop mode external clock
744 1m 0000 + IFC "",""
745 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
746 3m 0000 0000 +.STEXT SET .B0
747 4m 0000 + ENDC
748 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
749 6m 0000 0001 +_STEXT SET _B0
750 7m 0000 + ENDC
751 8m 0000 + ENDC
752 9m 0000 + IFNC "",""
753 10m 0000 +.STEXT SET .B0
754 11m 0000 +STEXT_ SET _B0
755 12m 0000 +STEXT_MSK SET (MSK)<<.B0
756 13m 0000 + IFC "",""
757 14m 0000 +STEXT_NMSK SET (-STEXT_MSK-1)&MSK16
758 15m 0000 + ENDC
759 16m 0000 + IFNC "",""
760 17m 0000 +STEXT_NMSK SET (-STEXT_MSK-1)&
761 18m 0000 + ENDC
762 19m 0000 + ENDC
763 143i 0000 |*-------------------------------------------------------------------*
764 144i 0000 |*UNUSED EQU $006 Unused position (BYTE)
765 145i 0000 |*-------------------------------------------------------------------*
766 146i 0000 0007 |RSR EQU $007 Reset Status Register (BYTE)
767 147i 0000 |* NOTE: RSR is a READ-ONLY register!
768 148i 0000 | DEF EXT,B7 . external reset
769 1m 0000 + IFC "",""
770 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
771 3m 0000 0007 +.EXT SET .B7
772 4m 0000 + ENDC
773 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
774 6m 0000 0080 +_EXT SET _B7
775 7m 0000 + ENDC
776 8m 0000 + ENDC
777 9m 0000 + IFNC "",""
778 10m 0000 +.EXT SET .B7
779 11m 0000 +EXT_ SET _B7
780 12m 0000 +EXT_MSK SET (MSK)<<.B7
781 13m 0000 + IFC "",""
782 14m 0000 +EXT_NMSK SET (-EXT_MSK-1)&MSK16
783 15m 0000 + ENDC
784 16m 0000 + IFNC "",""
785 17m 0000 +EXT_NMSK SET (-EXT_MSK-1)&
786 18m 0000 + ENDC
787 19m 0000 + ENDC
788 149i 0000 | DEF POW,B6 . powerup reset
789 1m 0000 + IFC "",""
790 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
791 3m 0000 0006 +.POW SET .B6
792 4m 0000 + ENDC
793 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
794 6m 0000 0040 +_POW SET _B6
795 7m 0000 + ENDC
796 8m 0000 + ENDC
797 9m 0000 + IFNC "",""
798 10m 0000 +.POW SET .B6
799 11m 0000 +POW_ SET _B6
800 12m 0000 +POW_MSK SET (MSK)<<.B6
801 13m 0000 + IFC "",""
802 14m 0000 +POW_NMSK SET (-POW_MSK-1)&MSK16
803 15m 0000 + ENDC
804 16m 0000 + IFNC "",""
805 17m 0000 +POW_NMSK SET (-POW_MSK-1)&
806 18m 0000 + ENDC
807 19m 0000 + ENDC
808 150i 0000 | DEF SW,B5 . software watchdog reset
809 1m 0000 + IFC "",""
810 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
811 3m 0000 0005 +.SW SET .B5
812 4m 0000 + ENDC
813 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
814 6m 0000 0020 +_SW SET _B5
815 7m 0000 + ENDC
816 8m 0000 + ENDC
817 9m 0000 + IFNC "",""
818 10m 0000 +.SW SET .B5
819 11m 0000 +SW_ SET _B5
820 12m 0000 +SW_MSK SET (MSK)<<.B5
821 13m 0000 + IFC "",""
822 14m 0000 +SW_NMSK SET (-SW_MSK-1)&MSK16
823 15m 0000 + ENDC
824 16m 0000 + IFNC "",""
825 17m 0000 +SW_NMSK SET (-SW_MSK-1)&
826 18m 0000 + ENDC
827 19m 0000 + ENDC
828 151i 0000 | DEF HLT,B4 . halt monitor reset
829 1m 0000 + IFC "",""
830 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
831 3m 0000 0004 +.HLT SET .B4
832 4m 0000 + ENDC
833 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
834 6m 0000 0010 +_HLT SET _B4
835 7m 0000 + ENDC
836 8m 0000 + ENDC
837 9m 0000 + IFNC "",""
838 10m 0000 +.HLT SET .B4
839 11m 0000 +HLT_ SET _B4
840 12m 0000 +HLT_MSK SET (MSK)<<.B4
841 13m 0000 + IFC "",""
842 14m 0000 +HLT_NMSK SET (-HLT_MSK-1)&MSK16
843 15m 0000 + ENDC
844 16m 0000 + IFNC "",""
845 17m 0000 +HLT_NMSK SET (-HLT_MSK-1)&
846 18m 0000 + ENDC
847 19m 0000 + ENDC
848 152i 0000 | DEF LOC,B2 . loss of clock reset
849 1m 0000 + IFC "",""
850 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
851 3m 0000 0002 +.LOC SET .B2
852 4m 0000 + ENDC
853 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
854 6m 0000 0004 +_LOC SET _B2
855 7m 0000 + ENDC
856 8m 0000 + ENDC
857 9m 0000 + IFNC "",""
858 10m 0000 +.LOC SET .B2
859 11m 0000 +LOC_ SET _B2
860 12m 0000 +LOC_MSK SET (MSK)<<.B2
861 13m 0000 + IFC "",""
862 14m 0000 +LOC_NMSK SET (-LOC_MSK-1)&MSK16
863 15m 0000 + ENDC
864 16m 0000 + IFNC "",""
865 17m 0000 +LOC_NMSK SET (-LOC_MSK-1)&
866 18m 0000 + ENDC
867 19m 0000 + ENDC
868 153i 0000 | DEF SYS,B1 . system reset
869 1m 0000 + IFC "",""
870 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
871 3m 0000 0001 +.SYS SET .B1
872 4m 0000 + ENDC
873 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
874 6m 0000 0002 +_SYS SET _B1
875 7m 0000 + ENDC
876 8m 0000 + ENDC
877 9m 0000 + IFNC "",""
878 10m 0000 +.SYS SET .B1
879 11m 0000 +SYS_ SET _B1
880 12m 0000 +SYS_MSK SET (MSK)<<.B1
881 13m 0000 + IFC "",""
882 14m 0000 +SYS_NMSK SET (-SYS_MSK-1)&MSK16
883 15m 0000 + ENDC
884 16m 0000 + IFNC "",""
885 17m 0000 +SYS_NMSK SET (-SYS_MSK-1)&
886 18m 0000 + ENDC
887 19m 0000 + ENDC
888 154i 0000 | DEF TST,B0 . test submodule reset
889 1m 0000 + IFC "",""
890 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
891 3m 0000 0000 +.TST SET .B0
892 4m 0000 + ENDC
893 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
894 6m 0000 0001 +_TST SET _B0
895 7m 0000 + ENDC
896 8m 0000 + ENDC
897 9m 0000 + IFNC "",""
898 10m 0000 +.TST SET .B0
899 11m 0000 +TST_ SET _B0
900 12m 0000 +TST_MSK SET (MSK)<<.B0
901 13m 0000 + IFC "",""
902 14m 0000 +TST_NMSK SET (-TST_MSK-1)&MSK16
903 15m 0000 + ENDC
904 16m 0000 + IFNC "",""
905 17m 0000 +TST_NMSK SET (-TST_MSK-1)&
906 18m 0000 + ENDC
907 19m 0000 + ENDC
908 155i 0000 |*-------------------------------------------------------------------*
909 156i 0000 0008 |SIMTRE EQU $008 System Integration Module Test E Register
910 157i 0000 |* NOTE: SIMTRE is a WRITE-ONLY register reserved for Factory Testing!
911 158i 0000 |*-------------------------------------------------------------------*
912 159i 0000 |*UNUSED EQU $00A Unused position
913 160i 0000 |*-------------------------------------------------------------------*
914 161i 0000 |*UNUSED EQU $00C Unused position
915 162i 0000 |*-------------------------------------------------------------------*
916 163i 0000 |*UNUSED EQU $00E Unused position
917 164i 0000 |*-------------------------------------------------------------------*
918 165i 0000 |*UNUSED EQU $010 Unused position (BYTE)
919 166i 0000 |*-------------------------------------------------------------------*
920 167i 0000 0011 |PORTE EQU $011 Port E Data Register (BYTE)
921 168i 0000 | DEF PE7,B7 . port E data bit 7
922 1m 0000 + IFC "",""
923 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
924 3m 0000 0007 +.PE7 SET .B7
925 4m 0000 + ENDC
926 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
927 6m 0000 0080 +_PE7 SET _B7
928 7m 0000 + ENDC
929 8m 0000 + ENDC
930 9m 0000 + IFNC "",""
931 10m 0000 +.PE7 SET .B7
932 11m 0000 +PE7_ SET _B7
933 12m 0000 +PE7_MSK SET (MSK)<<.B7
934 13m 0000 + IFC "",""
935 14m 0000 +PE7_NMSK SET (-PE7_MSK-1)&MSK16
936 15m 0000 + ENDC
937 16m 0000 + IFNC "",""
938 17m 0000 +PE7_NMSK SET (-PE7_MSK-1)&
939 18m 0000 + ENDC
940 19m 0000 + ENDC
941 169i 0000 | DEF PE6,B6 . port E data bit 6
942 1m 0000 + IFC "",""
943 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
944 3m 0000 0006 +.PE6 SET .B6
945 4m 0000 + ENDC
946 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
947 6m 0000 0040 +_PE6 SET _B6
948 7m 0000 + ENDC
949 8m 0000 + ENDC
950 9m 0000 + IFNC "",""
951 10m 0000 +.PE6 SET .B6
952 11m 0000 +PE6_ SET _B6
953 12m 0000 +PE6_MSK SET (MSK)<<.B6
954 13m 0000 + IFC "",""
955 14m 0000 +PE6_NMSK SET (-PE6_MSK-1)&MSK16
956 15m 0000 + ENDC
957 16m 0000 + IFNC "",""
958 17m 0000 +PE6_NMSK SET (-PE6_MSK-1)&
959 18m 0000 + ENDC
960 19m 0000 + ENDC
961 170i 0000 | DEF PE5,B5 . port E data bit 5
962 1m 0000 + IFC "",""
963 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
964 3m 0000 0005 +.PE5 SET .B5
965 4m 0000 + ENDC
966 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
967 6m 0000 0020 +_PE5 SET _B5
968 7m 0000 + ENDC
969 8m 0000 + ENDC
970 9m 0000 + IFNC "",""
971 10m 0000 +.PE5 SET .B5
972 11m 0000 +PE5_ SET _B5
973 12m 0000 +PE5_MSK SET (MSK)<<.B5
974 13m 0000 + IFC "",""
975 14m 0000 +PE5_NMSK SET (-PE5_MSK-1)&MSK16
976 15m 0000 + ENDC
977 16m 0000 + IFNC "",""
978 17m 0000 +PE5_NMSK SET (-PE5_MSK-1)&
979 18m 0000 + ENDC
980 19m 0000 + ENDC
981 171i 0000 | DEF PE4,B4 . port E data bit 4
982 1m 0000 + IFC "",""
983 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
984 3m 0000 0004 +.PE4 SET .B4
985 4m 0000 + ENDC
986 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
987 6m 0000 0010 +_PE4 SET _B4
988 7m 0000 + ENDC
989 8m 0000 + ENDC
990 9m 0000 + IFNC "",""
991 10m 0000 +.PE4 SET .B4
992 11m 0000 +PE4_ SET _B4
993 12m 0000 +PE4_MSK SET (MSK)<<.B4
994 13m 0000 + IFC "",""
995 14m 0000 +PE4_NMSK SET (-PE4_MSK-1)&MSK16
996 15m 0000 + ENDC
997 16m 0000 + IFNC "",""
998 17m 0000 +PE4_NMSK SET (-PE4_MSK-1)&
999 18m 0000 + ENDC
1000 19m 0000 + ENDC
1001 172i 0000 | DEF PE3,B3 . port E data bit 3
1002 1m 0000 + IFC "",""
1003 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1004 3m 0000 0003 +.PE3 SET .B3
1005 4m 0000 + ENDC
1006 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1007 6m 0000 0008 +_PE3 SET _B3
1008 7m 0000 + ENDC
1009 8m 0000 + ENDC
1010 9m 0000 + IFNC "",""
1011 10m 0000 +.PE3 SET .B3
1012 11m 0000 +PE3_ SET _B3
1013 12m 0000 +PE3_MSK SET (MSK)<<.B3
1014 13m 0000 + IFC "",""
1015 14m 0000 +PE3_NMSK SET (-PE3_MSK-1)&MSK16
1016 15m 0000 + ENDC
1017 16m 0000 + IFNC "",""
1018 17m 0000 +PE3_NMSK SET (-PE3_MSK-1)&
1019 18m 0000 + ENDC
1020 19m 0000 + ENDC
1021 173i 0000 | DEF PE2,B2 . port E data bit 2
1022 1m 0000 + IFC "",""
1023 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1024 3m 0000 0002 +.PE2 SET .B2
1025 4m 0000 + ENDC
1026 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1027 6m 0000 0004 +_PE2 SET _B2
1028 7m 0000 + ENDC
1029 8m 0000 + ENDC
1030 9m 0000 + IFNC "",""
1031 10m 0000 +.PE2 SET .B2
1032 11m 0000 +PE2_ SET _B2
1033 12m 0000 +PE2_MSK SET (MSK)<<.B2
1034 13m 0000 + IFC "",""
1035 14m 0000 +PE2_NMSK SET (-PE2_MSK-1)&MSK16
1036 15m 0000 + ENDC
1037 16m 0000 + IFNC "",""
1038 17m 0000 +PE2_NMSK SET (-PE2_MSK-1)&
1039 18m 0000 + ENDC
1040 19m 0000 + ENDC
1041 174i 0000 | DEF PE1,B1 . port E data bit 1
1042 1m 0000 + IFC "",""
1043 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1044 3m 0000 0001 +.PE1 SET .B1
1045 4m 0000 + ENDC
1046 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1047 6m 0000 0002 +_PE1 SET _B1
1048 7m 0000 + ENDC
1049 8m 0000 + ENDC
1050 9m 0000 + IFNC "",""
1051 10m 0000 +.PE1 SET .B1
1052 11m 0000 +PE1_ SET _B1
1053 12m 0000 +PE1_MSK SET (MSK)<<.B1
1054 13m 0000 + IFC "",""
1055 14m 0000 +PE1_NMSK SET (-PE1_MSK-1)&MSK16
1056 15m 0000 + ENDC
1057 16m 0000 + IFNC "",""
1058 17m 0000 +PE1_NMSK SET (-PE1_MSK-1)&
1059 18m 0000 + ENDC
1060 19m 0000 + ENDC
1061 175i 0000 | DEF PE0,B0 . port E data bit 0
1062 1m 0000 + IFC "",""
1063 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1064 3m 0000 0000 +.PE0 SET .B0
1065 4m 0000 + ENDC
1066 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1067 6m 0000 0001 +_PE0 SET _B0
1068 7m 0000 + ENDC
1069 8m 0000 + ENDC
1070 9m 0000 + IFNC "",""
1071 10m 0000 +.PE0 SET .B0
1072 11m 0000 +PE0_ SET _B0
1073 12m 0000 +PE0_MSK SET (MSK)<<.B0
1074 13m 0000 + IFC "",""
1075 14m 0000 +PE0_NMSK SET (-PE0_MSK-1)&MSK16
1076 15m 0000 + ENDC
1077 16m 0000 + IFNC "",""
1078 17m 0000 +PE0_NMSK SET (-PE0_MSK-1)&
1079 18m 0000 + ENDC
1080 19m 0000 + ENDC
1081 176i 0000 |*-------------------------------------------------------------------*
1082 177i 0000 |*UNUSED EQU $012 Unused position (BYTE)
1083 178i 0000 |*-------------------------------------------------------------------*
1084 179i 0000 0013 |PORTE1 EQU $013 Port E Data Register 1 (BYTE)
1085 180i 0000 |*-------------------------------------------------------------------*
1086 181i 0000 |*UNUSED EQU $014 Unused position (BYTE)
1087 182i 0000 |*-------------------------------------------------------------------*
1088 183i 0000 0015 |DDRE EQU $015 Port E Data Direction Register (BYTE)
1089 184i 0000 | DEF DDE7,B7 . port E data direction bit 7
1090 1m 0000 + IFC "",""
1091 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1092 3m 0000 0007 +.DDE7 SET .B7
1093 4m 0000 + ENDC
1094 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1095 6m 0000 0080 +_DDE7 SET _B7
1096 7m 0000 + ENDC
1097 8m 0000 + ENDC
1098 9m 0000 + IFNC "",""
1099 10m 0000 +.DDE7 SET .B7
1100 11m 0000 +DDE7_ SET _B7
1101 12m 0000 +DDE7_MSK SET (MSK)<<.B7
1102 13m 0000 + IFC "",""
1103 14m 0000 +DDE7_NMSK SET (-DDE7_MSK-1)&MSK16
1104 15m 0000 + ENDC
1105 16m 0000 + IFNC "",""
1106 17m 0000 +DDE7_NMSK SET (-DDE7_MSK-1)&
1107 18m 0000 + ENDC
1108 19m 0000 + ENDC
1109 185i 0000 | DEF DDE6,B6 . port E data direction bit 6
1110 1m 0000 + IFC "",""
1111 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1112 3m 0000 0006 +.DDE6 SET .B6
1113 4m 0000 + ENDC
1114 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1115 6m 0000 0040 +_DDE6 SET _B6
1116 7m 0000 + ENDC
1117 8m 0000 + ENDC
1118 9m 0000 + IFNC "",""
1119 10m 0000 +.DDE6 SET .B6
1120 11m 0000 +DDE6_ SET _B6
1121 12m 0000 +DDE6_MSK SET (MSK)<<.B6
1122 13m 0000 + IFC "",""
1123 14m 0000 +DDE6_NMSK SET (-DDE6_MSK-1)&MSK16
1124 15m 0000 + ENDC
1125 16m 0000 + IFNC "",""
1126 17m 0000 +DDE6_NMSK SET (-DDE6_MSK-1)&
1127 18m 0000 + ENDC
1128 19m 0000 + ENDC
1129 186i 0000 | DEF DDE5,B5 . port E data direction bit 5
1130 1m 0000 + IFC "",""
1131 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1132 3m 0000 0005 +.DDE5 SET .B5
1133 4m 0000 + ENDC
1134 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1135 6m 0000 0020 +_DDE5 SET _B5
1136 7m 0000 + ENDC
1137 8m 0000 + ENDC
1138 9m 0000 + IFNC "",""
1139 10m 0000 +.DDE5 SET .B5
1140 11m 0000 +DDE5_ SET _B5
1141 12m 0000 +DDE5_MSK SET (MSK)<<.B5
1142 13m 0000 + IFC "",""
1143 14m 0000 +DDE5_NMSK SET (-DDE5_MSK-1)&MSK16
1144 15m 0000 + ENDC
1145 16m 0000 + IFNC "",""
1146 17m 0000 +DDE5_NMSK SET (-DDE5_MSK-1)&
1147 18m 0000 + ENDC
1148 19m 0000 + ENDC
1149 187i 0000 | DEF DDE4,B4 . port E data direction bit 4
1150 1m 0000 + IFC "",""
1151 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1152 3m 0000 0004 +.DDE4 SET .B4
1153 4m 0000 + ENDC
1154 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1155 6m 0000 0010 +_DDE4 SET _B4
1156 7m 0000 + ENDC
1157 8m 0000 + ENDC
1158 9m 0000 + IFNC "",""
1159 10m 0000 +.DDE4 SET .B4
1160 11m 0000 +DDE4_ SET _B4
1161 12m 0000 +DDE4_MSK SET (MSK)<<.B4
1162 13m 0000 + IFC "",""
1163 14m 0000 +DDE4_NMSK SET (-DDE4_MSK-1)&MSK16
1164 15m 0000 + ENDC
1165 16m 0000 + IFNC "",""
1166 17m 0000 +DDE4_NMSK SET (-DDE4_MSK-1)&
1167 18m 0000 + ENDC
1168 19m 0000 + ENDC
1169 188i 0000 | DEF DDE3,B3 . port E data direction bit 3
1170 1m 0000 + IFC "",""
1171 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1172 3m 0000 0003 +.DDE3 SET .B3
1173 4m 0000 + ENDC
1174 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1175 6m 0000 0008 +_DDE3 SET _B3
1176 7m 0000 + ENDC
1177 8m 0000 + ENDC
1178 9m 0000 + IFNC "",""
1179 10m 0000 +.DDE3 SET .B3
1180 11m 0000 +DDE3_ SET _B3
1181 12m 0000 +DDE3_MSK SET (MSK)<<.B3
1182 13m 0000 + IFC "",""
1183 14m 0000 +DDE3_NMSK SET (-DDE3_MSK-1)&MSK16
1184 15m 0000 + ENDC
1185 16m 0000 + IFNC "",""
1186 17m 0000 +DDE3_NMSK SET (-DDE3_MSK-1)&
1187 18m 0000 + ENDC
1188 19m 0000 + ENDC
1189 189i 0000 | DEF DDE2,B2 . port E data direction bit 2
1190 1m 0000 + IFC "",""
1191 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1192 3m 0000 0002 +.DDE2 SET .B2
1193 4m 0000 + ENDC
1194 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1195 6m 0000 0004 +_DDE2 SET _B2
1196 7m 0000 + ENDC
1197 8m 0000 + ENDC
1198 9m 0000 + IFNC "",""
1199 10m 0000 +.DDE2 SET .B2
1200 11m 0000 +DDE2_ SET _B2
1201 12m 0000 +DDE2_MSK SET (MSK)<<.B2
1202 13m 0000 + IFC "",""
1203 14m 0000 +DDE2_NMSK SET (-DDE2_MSK-1)&MSK16
1204 15m 0000 + ENDC
1205 16m 0000 + IFNC "",""
1206 17m 0000 +DDE2_NMSK SET (-DDE2_MSK-1)&
1207 18m 0000 + ENDC
1208 19m 0000 + ENDC
1209 190i 0000 | DEF DDE1,B1 . port E data direction bit 1
1210 1m 0000 + IFC "",""
1211 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1212 3m 0000 0001 +.DDE1 SET .B1
1213 4m 0000 + ENDC
1214 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1215 6m 0000 0002 +_DDE1 SET _B1
1216 7m 0000 + ENDC
1217 8m 0000 + ENDC
1218 9m 0000 + IFNC "",""
1219 10m 0000 +.DDE1 SET .B1
1220 11m 0000 +DDE1_ SET _B1
1221 12m 0000 +DDE1_MSK SET (MSK)<<.B1
1222 13m 0000 + IFC "",""
1223 14m 0000 +DDE1_NMSK SET (-DDE1_MSK-1)&MSK16
1224 15m 0000 + ENDC
1225 16m 0000 + IFNC "",""
1226 17m 0000 +DDE1_NMSK SET (-DDE1_MSK-1)&
1227 18m 0000 + ENDC
1228 19m 0000 + ENDC
1229 191i 0000 | DEF DDE0,B0 . port E data direction bit 0
1230 1m 0000 + IFC "",""
1231 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1232 3m 0000 0000 +.DDE0 SET .B0
1233 4m 0000 + ENDC
1234 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1235 6m 0000 0001 +_DDE0 SET _B0
1236 7m 0000 + ENDC
1237 8m 0000 + ENDC
1238 9m 0000 + IFNC "",""
1239 10m 0000 +.DDE0 SET .B0
1240 11m 0000 +DDE0_ SET _B0
1241 12m 0000 +DDE0_MSK SET (MSK)<<.B0
1242 13m 0000 + IFC "",""
1243 14m 0000 +DDE0_NMSK SET (-DDE0_MSK-1)&MSK16
1244 15m 0000 + ENDC
1245 16m 0000 + IFNC "",""
1246 17m 0000 +DDE0_NMSK SET (-DDE0_MSK-1)&
1247 18m 0000 + ENDC
1248 19m 0000 + ENDC
1249 192i 0000 |*-------------------------------------------------------------------*
1250 193i 0000 |*UNUSED EQU $016 Unused position (BYTE)
1251 194i 0000 |*-------------------------------------------------------------------*
1252 195i 0000 0017 |PEPAR EQU $017 Port E Pin Assignment Register (BYTE)
1253 196i 0000 | DEF PEPA7,B7 . port E pin assignment bit 7
1254 1m 0000 + IFC "",""
1255 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1256 3m 0000 0007 +.PEPA7 SET .B7
1257 4m 0000 + ENDC
1258 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1259 6m 0000 0080 +_PEPA7 SET _B7
1260 7m 0000 + ENDC
1261 8m 0000 + ENDC
1262 9m 0000 + IFNC "",""
1263 10m 0000 +.PEPA7 SET .B7
1264 11m 0000 +PEPA7_ SET _B7
1265 12m 0000 +PEPA7_MSK SET (MSK)<<.B7
1266 13m 0000 + IFC "",""
1267 14m 0000 +PEPA7_NMSK SET (-PEPA7_MSK-1)&MSK16
1268 15m 0000 + ENDC
1269 16m 0000 + IFNC "",""
1270 17m 0000 +PEPA7_NMSK SET (-PEPA7_MSK-1)&
1271 18m 0000 + ENDC
1272 19m 0000 + ENDC
1273 197i 0000 | DEF PEPA6,B6 . port E pin assignment bit 6
1274 1m 0000 + IFC "",""
1275 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1276 3m 0000 0006 +.PEPA6 SET .B6
1277 4m 0000 + ENDC
1278 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1279 6m 0000 0040 +_PEPA6 SET _B6
1280 7m 0000 + ENDC
1281 8m 0000 + ENDC
1282 9m 0000 + IFNC "",""
1283 10m 0000 +.PEPA6 SET .B6
1284 11m 0000 +PEPA6_ SET _B6
1285 12m 0000 +PEPA6_MSK SET (MSK)<<.B6
1286 13m 0000 + IFC "",""
1287 14m 0000 +PEPA6_NMSK SET (-PEPA6_MSK-1)&MSK16
1288 15m 0000 + ENDC
1289 16m 0000 + IFNC "",""
1290 17m 0000 +PEPA6_NMSK SET (-PEPA6_MSK-1)&
1291 18m 0000 + ENDC
1292 19m 0000 + ENDC
1293 198i 0000 | DEF PEPA5,B5 . port E pin assignment bit 5
1294 1m 0000 + IFC "",""
1295 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1296 3m 0000 0005 +.PEPA5 SET .B5
1297 4m 0000 + ENDC
1298 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1299 6m 0000 0020 +_PEPA5 SET _B5
1300 7m 0000 + ENDC
1301 8m 0000 + ENDC
1302 9m 0000 + IFNC "",""
1303 10m 0000 +.PEPA5 SET .B5
1304 11m 0000 +PEPA5_ SET _B5
1305 12m 0000 +PEPA5_MSK SET (MSK)<<.B5
1306 13m 0000 + IFC "",""
1307 14m 0000 +PEPA5_NMSK SET (-PEPA5_MSK-1)&MSK16
1308 15m 0000 + ENDC
1309 16m 0000 + IFNC "",""
1310 17m 0000 +PEPA5_NMSK SET (-PEPA5_MSK-1)&
1311 18m 0000 + ENDC
1312 19m 0000 + ENDC
1313 199i 0000 | DEF PEPA4,B4 . port E pin assignment bit 4
1314 1m 0000 + IFC "",""
1315 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1316 3m 0000 0004 +.PEPA4 SET .B4
1317 4m 0000 + ENDC
1318 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1319 6m 0000 0010 +_PEPA4 SET _B4
1320 7m 0000 + ENDC
1321 8m 0000 + ENDC
1322 9m 0000 + IFNC "",""
1323 10m 0000 +.PEPA4 SET .B4
1324 11m 0000 +PEPA4_ SET _B4
1325 12m 0000 +PEPA4_MSK SET (MSK)<<.B4
1326 13m 0000 + IFC "",""
1327 14m 0000 +PEPA4_NMSK SET (-PEPA4_MSK-1)&MSK16
1328 15m 0000 + ENDC
1329 16m 0000 + IFNC "",""
1330 17m 0000 +PEPA4_NMSK SET (-PEPA4_MSK-1)&
1331 18m 0000 + ENDC
1332 19m 0000 + ENDC
1333 200i 0000 | DEF PEPA3,B3 . port E pin assignment bit 3
1334 1m 0000 + IFC "",""
1335 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1336 3m 0000 0003 +.PEPA3 SET .B3
1337 4m 0000 + ENDC
1338 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1339 6m 0000 0008 +_PEPA3 SET _B3
1340 7m 0000 + ENDC
1341 8m 0000 + ENDC
1342 9m 0000 + IFNC "",""
1343 10m 0000 +.PEPA3 SET .B3
1344 11m 0000 +PEPA3_ SET _B3
1345 12m 0000 +PEPA3_MSK SET (MSK)<<.B3
1346 13m 0000 + IFC "",""
1347 14m 0000 +PEPA3_NMSK SET (-PEPA3_MSK-1)&MSK16
1348 15m 0000 + ENDC
1349 16m 0000 + IFNC "",""
1350 17m 0000 +PEPA3_NMSK SET (-PEPA3_MSK-1)&
1351 18m 0000 + ENDC
1352 19m 0000 + ENDC
1353 201i 0000 | DEF PEPA2,B2 . port E pin assignment bit 2
1354 1m 0000 + IFC "",""
1355 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1356 3m 0000 0002 +.PEPA2 SET .B2
1357 4m 0000 + ENDC
1358 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1359 6m 0000 0004 +_PEPA2 SET _B2
1360 7m 0000 + ENDC
1361 8m 0000 + ENDC
1362 9m 0000 + IFNC "",""
1363 10m 0000 +.PEPA2 SET .B2
1364 11m 0000 +PEPA2_ SET _B2
1365 12m 0000 +PEPA2_MSK SET (MSK)<<.B2
1366 13m 0000 + IFC "",""
1367 14m 0000 +PEPA2_NMSK SET (-PEPA2_MSK-1)&MSK16
1368 15m 0000 + ENDC
1369 16m 0000 + IFNC "",""
1370 17m 0000 +PEPA2_NMSK SET (-PEPA2_MSK-1)&
1371 18m 0000 + ENDC
1372 19m 0000 + ENDC
1373 202i 0000 | DEF PEPA1,B1 . port E pin assignment bit 1
1374 1m 0000 + IFC "",""
1375 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1376 3m 0000 0001 +.PEPA1 SET .B1
1377 4m 0000 + ENDC
1378 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1379 6m 0000 0002 +_PEPA1 SET _B1
1380 7m 0000 + ENDC
1381 8m 0000 + ENDC
1382 9m 0000 + IFNC "",""
1383 10m 0000 +.PEPA1 SET .B1
1384 11m 0000 +PEPA1_ SET _B1
1385 12m 0000 +PEPA1_MSK SET (MSK)<<.B1
1386 13m 0000 + IFC "",""
1387 14m 0000 +PEPA1_NMSK SET (-PEPA1_MSK-1)&MSK16
1388 15m 0000 + ENDC
1389 16m 0000 + IFNC "",""
1390 17m 0000 +PEPA1_NMSK SET (-PEPA1_MSK-1)&
1391 18m 0000 + ENDC
1392 19m 0000 + ENDC
1393 203i 0000 | DEF PEPA0,B0 . port E pin assignment bit 0
1394 1m 0000 + IFC "",""
1395 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1396 3m 0000 0000 +.PEPA0 SET .B0
1397 4m 0000 + ENDC
1398 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1399 6m 0000 0001 +_PEPA0 SET _B0
1400 7m 0000 + ENDC
1401 8m 0000 + ENDC
1402 9m 0000 + IFNC "",""
1403 10m 0000 +.PEPA0 SET .B0
1404 11m 0000 +PEPA0_ SET _B0
1405 12m 0000 +PEPA0_MSK SET (MSK)<<.B0
1406 13m 0000 + IFC "",""
1407 14m 0000 +PEPA0_NMSK SET (-PEPA0_MSK-1)&MSK16
1408 15m 0000 + ENDC
1409 16m 0000 + IFNC "",""
1410 17m 0000 +PEPA0_NMSK SET (-PEPA0_MSK-1)&
1411 18m 0000 + ENDC
1412 19m 0000 + ENDC
1413 204i 0000 |*-------------------------------------------------------------------*
1414 205i 0000 |*UNUSED EQU $018 Unused position (BYTE)
1415 206i 0000 |*-------------------------------------------------------------------*
1416 207i 0000 0019 |PORTF EQU $019 Port F Data Register (BYTE)
1417 208i 0000 | DEF PF7,B7 . port F data bit 7
1418 1m 0000 + IFC "",""
1419 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1420 3m 0000 0007 +.PF7 SET .B7
1421 4m 0000 + ENDC
1422 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1423 6m 0000 0080 +_PF7 SET _B7
1424 7m 0000 + ENDC
1425 8m 0000 + ENDC
1426 9m 0000 + IFNC "",""
1427 10m 0000 +.PF7 SET .B7
1428 11m 0000 +PF7_ SET _B7
1429 12m 0000 +PF7_MSK SET (MSK)<<.B7
1430 13m 0000 + IFC "",""
1431 14m 0000 +PF7_NMSK SET (-PF7_MSK-1)&MSK16
1432 15m 0000 + ENDC
1433 16m 0000 + IFNC "",""
1434 17m 0000 +PF7_NMSK SET (-PF7_MSK-1)&
1435 18m 0000 + ENDC
1436 19m 0000 + ENDC
1437 209i 0000 | DEF PF6,B6 . port F data bit 6
1438 1m 0000 + IFC "",""
1439 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1440 3m 0000 0006 +.PF6 SET .B6
1441 4m 0000 + ENDC
1442 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1443 6m 0000 0040 +_PF6 SET _B6
1444 7m 0000 + ENDC
1445 8m 0000 + ENDC
1446 9m 0000 + IFNC "",""
1447 10m 0000 +.PF6 SET .B6
1448 11m 0000 +PF6_ SET _B6
1449 12m 0000 +PF6_MSK SET (MSK)<<.B6
1450 13m 0000 + IFC "",""
1451 14m 0000 +PF6_NMSK SET (-PF6_MSK-1)&MSK16
1452 15m 0000 + ENDC
1453 16m 0000 + IFNC "",""
1454 17m 0000 +PF6_NMSK SET (-PF6_MSK-1)&
1455 18m 0000 + ENDC
1456 19m 0000 + ENDC
1457 210i 0000 | DEF PF5,B5 . port F data bit 5
1458 1m 0000 + IFC "",""
1459 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1460 3m 0000 0005 +.PF5 SET .B5
1461 4m 0000 + ENDC
1462 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1463 6m 0000 0020 +_PF5 SET _B5
1464 7m 0000 + ENDC
1465 8m 0000 + ENDC
1466 9m 0000 + IFNC "",""
1467 10m 0000 +.PF5 SET .B5
1468 11m 0000 +PF5_ SET _B5
1469 12m 0000 +PF5_MSK SET (MSK)<<.B5
1470 13m 0000 + IFC "",""
1471 14m 0000 +PF5_NMSK SET (-PF5_MSK-1)&MSK16
1472 15m 0000 + ENDC
1473 16m 0000 + IFNC "",""
1474 17m 0000 +PF5_NMSK SET (-PF5_MSK-1)&
1475 18m 0000 + ENDC
1476 19m 0000 + ENDC
1477 211i 0000 | DEF PF4,B4 . port F data bit 4
1478 1m 0000 + IFC "",""
1479 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1480 3m 0000 0004 +.PF4 SET .B4
1481 4m 0000 + ENDC
1482 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1483 6m 0000 0010 +_PF4 SET _B4
1484 7m 0000 + ENDC
1485 8m 0000 + ENDC
1486 9m 0000 + IFNC "",""
1487 10m 0000 +.PF4 SET .B4
1488 11m 0000 +PF4_ SET _B4
1489 12m 0000 +PF4_MSK SET (MSK)<<.B4
1490 13m 0000 + IFC "",""
1491 14m 0000 +PF4_NMSK SET (-PF4_MSK-1)&MSK16
1492 15m 0000 + ENDC
1493 16m 0000 + IFNC "",""
1494 17m 0000 +PF4_NMSK SET (-PF4_MSK-1)&
1495 18m 0000 + ENDC
1496 19m 0000 + ENDC
1497 212i 0000 | DEF PF3,B3 . port F data bit 3
1498 1m 0000 + IFC "",""
1499 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1500 3m 0000 0003 +.PF3 SET .B3
1501 4m 0000 + ENDC
1502 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1503 6m 0000 0008 +_PF3 SET _B3
1504 7m 0000 + ENDC
1505 8m 0000 + ENDC
1506 9m 0000 + IFNC "",""
1507 10m 0000 +.PF3 SET .B3
1508 11m 0000 +PF3_ SET _B3
1509 12m 0000 +PF3_MSK SET (MSK)<<.B3
1510 13m 0000 + IFC "",""
1511 14m 0000 +PF3_NMSK SET (-PF3_MSK-1)&MSK16
1512 15m 0000 + ENDC
1513 16m 0000 + IFNC "",""
1514 17m 0000 +PF3_NMSK SET (-PF3_MSK-1)&
1515 18m 0000 + ENDC
1516 19m 0000 + ENDC
1517 213i 0000 | DEF PF2,B2 . port F data bit 2
1518 1m 0000 + IFC "",""
1519 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1520 3m 0000 0002 +.PF2 SET .B2
1521 4m 0000 + ENDC
1522 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1523 6m 0000 0004 +_PF2 SET _B2
1524 7m 0000 + ENDC
1525 8m 0000 + ENDC
1526 9m 0000 + IFNC "",""
1527 10m 0000 +.PF2 SET .B2
1528 11m 0000 +PF2_ SET _B2
1529 12m 0000 +PF2_MSK SET (MSK)<<.B2
1530 13m 0000 + IFC "",""
1531 14m 0000 +PF2_NMSK SET (-PF2_MSK-1)&MSK16
1532 15m 0000 + ENDC
1533 16m 0000 + IFNC "",""
1534 17m 0000 +PF2_NMSK SET (-PF2_MSK-1)&
1535 18m 0000 + ENDC
1536 19m 0000 + ENDC
1537 214i 0000 | DEF PF1,B1 . port F data bit 1
1538 1m 0000 + IFC "",""
1539 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1540 3m 0000 0001 +.PF1 SET .B1
1541 4m 0000 + ENDC
1542 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1543 6m 0000 0002 +_PF1 SET _B1
1544 7m 0000 + ENDC
1545 8m 0000 + ENDC
1546 9m 0000 + IFNC "",""
1547 10m 0000 +.PF1 SET .B1
1548 11m 0000 +PF1_ SET _B1
1549 12m 0000 +PF1_MSK SET (MSK)<<.B1
1550 13m 0000 + IFC "",""
1551 14m 0000 +PF1_NMSK SET (-PF1_MSK-1)&MSK16
1552 15m 0000 + ENDC
1553 16m 0000 + IFNC "",""
1554 17m 0000 +PF1_NMSK SET (-PF1_MSK-1)&
1555 18m 0000 + ENDC
1556 19m 0000 + ENDC
1557 215i 0000 | DEF PF0,B0 . port F data bit 0
1558 1m 0000 + IFC "",""
1559 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1560 3m 0000 0000 +.PF0 SET .B0
1561 4m 0000 + ENDC
1562 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1563 6m 0000 0001 +_PF0 SET _B0
1564 7m 0000 + ENDC
1565 8m 0000 + ENDC
1566 9m 0000 + IFNC "",""
1567 10m 0000 +.PF0 SET .B0
1568 11m 0000 +PF0_ SET _B0
1569 12m 0000 +PF0_MSK SET (MSK)<<.B0
1570 13m 0000 + IFC "",""
1571 14m 0000 +PF0_NMSK SET (-PF0_MSK-1)&MSK16
1572 15m 0000 + ENDC
1573 16m 0000 + IFNC "",""
1574 17m 0000 +PF0_NMSK SET (-PF0_MSK-1)&
1575 18m 0000 + ENDC
1576 19m 0000 + ENDC
1577 216i 0000 |*-------------------------------------------------------------------*
1578 217i 0000 |*UNUSED EQU $01A Unused position (BYTE)
1579 218i 0000 |*-------------------------------------------------------------------*
1580 219i 0000 001B |PORTF1 EQU $01B Port F Data Register 1 (BYTE)
1581 220i 0000 |*-------------------------------------------------------------------*
1582 221i 0000 |*UNUSED EQU $01C Unused position (BYTE)
1583 222i 0000 |*-------------------------------------------------------------------*
1584 223i 0000 001D |DDRF EQU $01D Port F Data Direction Register (BYTE)
1585 224i 0000 | DEF DDF7,B7 . port F data direction bit 7
1586 1m 0000 + IFC "",""
1587 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1588 3m 0000 0007 +.DDF7 SET .B7
1589 4m 0000 + ENDC
1590 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1591 6m 0000 0080 +_DDF7 SET _B7
1592 7m 0000 + ENDC
1593 8m 0000 + ENDC
1594 9m 0000 + IFNC "",""
1595 10m 0000 +.DDF7 SET .B7
1596 11m 0000 +DDF7_ SET _B7
1597 12m 0000 +DDF7_MSK SET (MSK)<<.B7
1598 13m 0000 + IFC "",""
1599 14m 0000 +DDF7_NMSK SET (-DDF7_MSK-1)&MSK16
1600 15m 0000 + ENDC
1601 16m 0000 + IFNC "",""
1602 17m 0000 +DDF7_NMSK SET (-DDF7_MSK-1)&
1603 18m 0000 + ENDC
1604 19m 0000 + ENDC
1605 225i 0000 | DEF DDF6,B6 . port F data direction bit 6
1606 1m 0000 + IFC "",""
1607 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1608 3m 0000 0006 +.DDF6 SET .B6
1609 4m 0000 + ENDC
1610 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1611 6m 0000 0040 +_DDF6 SET _B6
1612 7m 0000 + ENDC
1613 8m 0000 + ENDC
1614 9m 0000 + IFNC "",""
1615 10m 0000 +.DDF6 SET .B6
1616 11m 0000 +DDF6_ SET _B6
1617 12m 0000 +DDF6_MSK SET (MSK)<<.B6
1618 13m 0000 + IFC "",""
1619 14m 0000 +DDF6_NMSK SET (-DDF6_MSK-1)&MSK16
1620 15m 0000 + ENDC
1621 16m 0000 + IFNC "",""
1622 17m 0000 +DDF6_NMSK SET (-DDF6_MSK-1)&
1623 18m 0000 + ENDC
1624 19m 0000 + ENDC
1625 226i 0000 | DEF DDF5,B5 . port F data direction bit 5
1626 1m 0000 + IFC "",""
1627 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1628 3m 0000 0005 +.DDF5 SET .B5
1629 4m 0000 + ENDC
1630 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1631 6m 0000 0020 +_DDF5 SET _B5
1632 7m 0000 + ENDC
1633 8m 0000 + ENDC
1634 9m 0000 + IFNC "",""
1635 10m 0000 +.DDF5 SET .B5
1636 11m 0000 +DDF5_ SET _B5
1637 12m 0000 +DDF5_MSK SET (MSK)<<.B5
1638 13m 0000 + IFC "",""
1639 14m 0000 +DDF5_NMSK SET (-DDF5_MSK-1)&MSK16
1640 15m 0000 + ENDC
1641 16m 0000 + IFNC "",""
1642 17m 0000 +DDF5_NMSK SET (-DDF5_MSK-1)&
1643 18m 0000 + ENDC
1644 19m 0000 + ENDC
1645 227i 0000 | DEF DDF4,B4 . port F data direction bit 4
1646 1m 0000 + IFC "",""
1647 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1648 3m 0000 0004 +.DDF4 SET .B4
1649 4m 0000 + ENDC
1650 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1651 6m 0000 0010 +_DDF4 SET _B4
1652 7m 0000 + ENDC
1653 8m 0000 + ENDC
1654 9m 0000 + IFNC "",""
1655 10m 0000 +.DDF4 SET .B4
1656 11m 0000 +DDF4_ SET _B4
1657 12m 0000 +DDF4_MSK SET (MSK)<<.B4
1658 13m 0000 + IFC "",""
1659 14m 0000 +DDF4_NMSK SET (-DDF4_MSK-1)&MSK16
1660 15m 0000 + ENDC
1661 16m 0000 + IFNC "",""
1662 17m 0000 +DDF4_NMSK SET (-DDF4_MSK-1)&
1663 18m 0000 + ENDC
1664 19m 0000 + ENDC
1665 228i 0000 | DEF DDF3,B3 . port F data direction bit 3
1666 1m 0000 + IFC "",""
1667 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1668 3m 0000 0003 +.DDF3 SET .B3
1669 4m 0000 + ENDC
1670 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1671 6m 0000 0008 +_DDF3 SET _B3
1672 7m 0000 + ENDC
1673 8m 0000 + ENDC
1674 9m 0000 + IFNC "",""
1675 10m 0000 +.DDF3 SET .B3
1676 11m 0000 +DDF3_ SET _B3
1677 12m 0000 +DDF3_MSK SET (MSK)<<.B3
1678 13m 0000 + IFC "",""
1679 14m 0000 +DDF3_NMSK SET (-DDF3_MSK-1)&MSK16
1680 15m 0000 + ENDC
1681 16m 0000 + IFNC "",""
1682 17m 0000 +DDF3_NMSK SET (-DDF3_MSK-1)&
1683 18m 0000 + ENDC
1684 19m 0000 + ENDC
1685 229i 0000 | DEF DDF2,B2 . port F data direction bit 2
1686 1m 0000 + IFC "",""
1687 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1688 3m 0000 0002 +.DDF2 SET .B2
1689 4m 0000 + ENDC
1690 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1691 6m 0000 0004 +_DDF2 SET _B2
1692 7m 0000 + ENDC
1693 8m 0000 + ENDC
1694 9m 0000 + IFNC "",""
1695 10m 0000 +.DDF2 SET .B2
1696 11m 0000 +DDF2_ SET _B2
1697 12m 0000 +DDF2_MSK SET (MSK)<<.B2
1698 13m 0000 + IFC "",""
1699 14m 0000 +DDF2_NMSK SET (-DDF2_MSK-1)&MSK16
1700 15m 0000 + ENDC
1701 16m 0000 + IFNC "",""
1702 17m 0000 +DDF2_NMSK SET (-DDF2_MSK-1)&
1703 18m 0000 + ENDC
1704 19m 0000 + ENDC
1705 230i 0000 | DEF DDF1,B1 . port F data direction bit 1
1706 1m 0000 + IFC "",""
1707 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1708 3m 0000 0001 +.DDF1 SET .B1
1709 4m 0000 + ENDC
1710 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1711 6m 0000 0002 +_DDF1 SET _B1
1712 7m 0000 + ENDC
1713 8m 0000 + ENDC
1714 9m 0000 + IFNC "",""
1715 10m 0000 +.DDF1 SET .B1
1716 11m 0000 +DDF1_ SET _B1
1717 12m 0000 +DDF1_MSK SET (MSK)<<.B1
1718 13m 0000 + IFC "",""
1719 14m 0000 +DDF1_NMSK SET (-DDF1_MSK-1)&MSK16
1720 15m 0000 + ENDC
1721 16m 0000 + IFNC "",""
1722 17m 0000 +DDF1_NMSK SET (-DDF1_MSK-1)&
1723 18m 0000 + ENDC
1724 19m 0000 + ENDC
1725 231i 0000 | DEF DDF0,B0 . port F data direction bit 0
1726 1m 0000 + IFC "",""
1727 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1728 3m 0000 0000 +.DDF0 SET .B0
1729 4m 0000 + ENDC
1730 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1731 6m 0000 0001 +_DDF0 SET _B0
1732 7m 0000 + ENDC
1733 8m 0000 + ENDC
1734 9m 0000 + IFNC "",""
1735 10m 0000 +.DDF0 SET .B0
1736 11m 0000 +DDF0_ SET _B0
1737 12m 0000 +DDF0_MSK SET (MSK)<<.B0
1738 13m 0000 + IFC "",""
1739 14m 0000 +DDF0_NMSK SET (-DDF0_MSK-1)&MSK16
1740 15m 0000 + ENDC
1741 16m 0000 + IFNC "",""
1742 17m 0000 +DDF0_NMSK SET (-DDF0_MSK-1)&
1743 18m 0000 + ENDC
1744 19m 0000 + ENDC
1745 232i 0000 |*-------------------------------------------------------------------*
1746 233i 0000 |*UNUSED EQU $01E Unused position (BYTE)
1747 234i 0000 |*-------------------------------------------------------------------*
1748 235i 0000 001F |PFPAR EQU $01F Port F Pin Assignment Register (BYTE)
1749 236i 0000 | DEF PFPA7,B7 . port F pin assignment bit 7
1750 1m 0000 + IFC "",""
1751 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1752 3m 0000 0007 +.PFPA7 SET .B7
1753 4m 0000 + ENDC
1754 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1755 6m 0000 0080 +_PFPA7 SET _B7
1756 7m 0000 + ENDC
1757 8m 0000 + ENDC
1758 9m 0000 + IFNC "",""
1759 10m 0000 +.PFPA7 SET .B7
1760 11m 0000 +PFPA7_ SET _B7
1761 12m 0000 +PFPA7_MSK SET (MSK)<<.B7
1762 13m 0000 + IFC "",""
1763 14m 0000 +PFPA7_NMSK SET (-PFPA7_MSK-1)&MSK16
1764 15m 0000 + ENDC
1765 16m 0000 + IFNC "",""
1766 17m 0000 +PFPA7_NMSK SET (-PFPA7_MSK-1)&
1767 18m 0000 + ENDC
1768 19m 0000 + ENDC
1769 237i 0000 | DEF PFPA6,B6 . port F pin assignment bit 6
1770 1m 0000 + IFC "",""
1771 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1772 3m 0000 0006 +.PFPA6 SET .B6
1773 4m 0000 + ENDC
1774 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1775 6m 0000 0040 +_PFPA6 SET _B6
1776 7m 0000 + ENDC
1777 8m 0000 + ENDC
1778 9m 0000 + IFNC "",""
1779 10m 0000 +.PFPA6 SET .B6
1780 11m 0000 +PFPA6_ SET _B6
1781 12m 0000 +PFPA6_MSK SET (MSK)<<.B6
1782 13m 0000 + IFC "",""
1783 14m 0000 +PFPA6_NMSK SET (-PFPA6_MSK-1)&MSK16
1784 15m 0000 + ENDC
1785 16m 0000 + IFNC "",""
1786 17m 0000 +PFPA6_NMSK SET (-PFPA6_MSK-1)&
1787 18m 0000 + ENDC
1788 19m 0000 + ENDC
1789 238i 0000 | DEF PFPA5,B5 . port F pin assignment bit 5
1790 1m 0000 + IFC "",""
1791 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1792 3m 0000 0005 +.PFPA5 SET .B5
1793 4m 0000 + ENDC
1794 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1795 6m 0000 0020 +_PFPA5 SET _B5
1796 7m 0000 + ENDC
1797 8m 0000 + ENDC
1798 9m 0000 + IFNC "",""
1799 10m 0000 +.PFPA5 SET .B5
1800 11m 0000 +PFPA5_ SET _B5
1801 12m 0000 +PFPA5_MSK SET (MSK)<<.B5
1802 13m 0000 + IFC "",""
1803 14m 0000 +PFPA5_NMSK SET (-PFPA5_MSK-1)&MSK16
1804 15m 0000 + ENDC
1805 16m 0000 + IFNC "",""
1806 17m 0000 +PFPA5_NMSK SET (-PFPA5_MSK-1)&
1807 18m 0000 + ENDC
1808 19m 0000 + ENDC
1809 239i 0000 | DEF PFPA4,B4 . port F pin assignment bit 4
1810 1m 0000 + IFC "",""
1811 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1812 3m 0000 0004 +.PFPA4 SET .B4
1813 4m 0000 + ENDC
1814 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1815 6m 0000 0010 +_PFPA4 SET _B4
1816 7m 0000 + ENDC
1817 8m 0000 + ENDC
1818 9m 0000 + IFNC "",""
1819 10m 0000 +.PFPA4 SET .B4
1820 11m 0000 +PFPA4_ SET _B4
1821 12m 0000 +PFPA4_MSK SET (MSK)<<.B4
1822 13m 0000 + IFC "",""
1823 14m 0000 +PFPA4_NMSK SET (-PFPA4_MSK-1)&MSK16
1824 15m 0000 + ENDC
1825 16m 0000 + IFNC "",""
1826 17m 0000 +PFPA4_NMSK SET (-PFPA4_MSK-1)&
1827 18m 0000 + ENDC
1828 19m 0000 + ENDC
1829 240i 0000 | DEF PFPA3,B3 . port F pin assignment bit 3
1830 1m 0000 + IFC "",""
1831 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1832 3m 0000 0003 +.PFPA3 SET .B3
1833 4m 0000 + ENDC
1834 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1835 6m 0000 0008 +_PFPA3 SET _B3
1836 7m 0000 + ENDC
1837 8m 0000 + ENDC
1838 9m 0000 + IFNC "",""
1839 10m 0000 +.PFPA3 SET .B3
1840 11m 0000 +PFPA3_ SET _B3
1841 12m 0000 +PFPA3_MSK SET (MSK)<<.B3
1842 13m 0000 + IFC "",""
1843 14m 0000 +PFPA3_NMSK SET (-PFPA3_MSK-1)&MSK16
1844 15m 0000 + ENDC
1845 16m 0000 + IFNC "",""
1846 17m 0000 +PFPA3_NMSK SET (-PFPA3_MSK-1)&
1847 18m 0000 + ENDC
1848 19m 0000 + ENDC
1849 241i 0000 | DEF PFPA2,B2 . port F pin assignment bit 2
1850 1m 0000 + IFC "",""
1851 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1852 3m 0000 0002 +.PFPA2 SET .B2
1853 4m 0000 + ENDC
1854 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1855 6m 0000 0004 +_PFPA2 SET _B2
1856 7m 0000 + ENDC
1857 8m 0000 + ENDC
1858 9m 0000 + IFNC "",""
1859 10m 0000 +.PFPA2 SET .B2
1860 11m 0000 +PFPA2_ SET _B2
1861 12m 0000 +PFPA2_MSK SET (MSK)<<.B2
1862 13m 0000 + IFC "",""
1863 14m 0000 +PFPA2_NMSK SET (-PFPA2_MSK-1)&MSK16
1864 15m 0000 + ENDC
1865 16m 0000 + IFNC "",""
1866 17m 0000 +PFPA2_NMSK SET (-PFPA2_MSK-1)&
1867 18m 0000 + ENDC
1868 19m 0000 + ENDC
1869 242i 0000 | DEF PFPA1,B1 . port F pin assignment bit 1
1870 1m 0000 + IFC "",""
1871 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1872 3m 0000 0001 +.PFPA1 SET .B1
1873 4m 0000 + ENDC
1874 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1875 6m 0000 0002 +_PFPA1 SET _B1
1876 7m 0000 + ENDC
1877 8m 0000 + ENDC
1878 9m 0000 + IFNC "",""
1879 10m 0000 +.PFPA1 SET .B1
1880 11m 0000 +PFPA1_ SET _B1
1881 12m 0000 +PFPA1_MSK SET (MSK)<<.B1
1882 13m 0000 + IFC "",""
1883 14m 0000 +PFPA1_NMSK SET (-PFPA1_MSK-1)&MSK16
1884 15m 0000 + ENDC
1885 16m 0000 + IFNC "",""
1886 17m 0000 +PFPA1_NMSK SET (-PFPA1_MSK-1)&
1887 18m 0000 + ENDC
1888 19m 0000 + ENDC
1889 243i 0000 | DEF PFPA0,B0 . port F pin assignment bit 0
1890 1m 0000 + IFC "",""
1891 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1892 3m 0000 0000 +.PFPA0 SET .B0
1893 4m 0000 + ENDC
1894 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1895 6m 0000 0001 +_PFPA0 SET _B0
1896 7m 0000 + ENDC
1897 8m 0000 + ENDC
1898 9m 0000 + IFNC "",""
1899 10m 0000 +.PFPA0 SET .B0
1900 11m 0000 +PFPA0_ SET _B0
1901 12m 0000 +PFPA0_MSK SET (MSK)<<.B0
1902 13m 0000 + IFC "",""
1903 14m 0000 +PFPA0_NMSK SET (-PFPA0_MSK-1)&MSK16
1904 15m 0000 + ENDC
1905 16m 0000 + IFNC "",""
1906 17m 0000 +PFPA0_NMSK SET (-PFPA0_MSK-1)&
1907 18m 0000 + ENDC
1908 19m 0000 + ENDC
1909 244i 0000 |*-------------------------------------------------------------------*
1910 245i 0000 |*UNUSED EQU $020 Unused position (BYTE)
1911 246i 0000 |*-------------------------------------------------------------------*
1912 247i 0000 0021 |SYPCR EQU $021 System Protection Register (BYTE)
1913 248i 0000 |* NOTE: SYPCR is a WRITE-ONCE register!
1914 249i 0000 | DEF SWE,B7 . software watchdog enable
1915 1m 0000 + IFC "",""
1916 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1917 3m 0000 0007 +.SWE SET .B7
1918 4m 0000 + ENDC
1919 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1920 6m 0000 0080 +_SWE SET _B7
1921 7m 0000 + ENDC
1922 8m 0000 + ENDC
1923 9m 0000 + IFNC "",""
1924 10m 0000 +.SWE SET .B7
1925 11m 0000 +SWE_ SET _B7
1926 12m 0000 +SWE_MSK SET (MSK)<<.B7
1927 13m 0000 + IFC "",""
1928 14m 0000 +SWE_NMSK SET (-SWE_MSK-1)&MSK16
1929 15m 0000 + ENDC
1930 16m 0000 + IFNC "",""
1931 17m 0000 +SWE_NMSK SET (-SWE_MSK-1)&
1932 18m 0000 + ENDC
1933 19m 0000 + ENDC
1934 250i 0000 | DEF SWP,B6 . software watchdog prescale
1935 1m 0000 + IFC "",""
1936 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1937 3m 0000 0006 +.SWP SET .B6
1938 4m 0000 + ENDC
1939 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1940 6m 0000 0040 +_SWP SET _B6
1941 7m 0000 + ENDC
1942 8m 0000 + ENDC
1943 9m 0000 + IFNC "",""
1944 10m 0000 +.SWP SET .B6
1945 11m 0000 +SWP_ SET _B6
1946 12m 0000 +SWP_MSK SET (MSK)<<.B6
1947 13m 0000 + IFC "",""
1948 14m 0000 +SWP_NMSK SET (-SWP_MSK-1)&MSK16
1949 15m 0000 + ENDC
1950 16m 0000 + IFNC "",""
1951 17m 0000 +SWP_NMSK SET (-SWP_MSK-1)&
1952 18m 0000 + ENDC
1953 19m 0000 + ENDC
1954 251i 0000 | DEF SWT,B4,2,MSK8 . software watchdog timing (2 bits)
1955 1m 0000 + IFC "","2"
1956 2m 0000 + IFNE BIT$CODE&BIT$NUM
1957 3m 0000 +.SWT SET .B4
1958 4m 0000 + ENDC
1959 5m 0000 + IFNE BIT$CODE&BIT$VAL
1960 6m 0000 +_SWT SET _B4
1961 7m 0000 + ENDC
1962 8m 0000 + ENDC
1963 9m 0000 + IFNC "","2"
1964 10m 0000 0004 +.SWT SET .B4
1965 11m 0000 0010 +SWT_ SET _B4
1966 12m 0000 0030 +SWT_MSK SET (MSK2)<<.B4
1967 13m 0000 + IFC "","MSK8"
1968 14m 0000 +SWT_NMSK SET (-SWT_MSK-1)&MSK16
1969 15m 0000 + ENDC
1970 16m 0000 + IFNC "","MSK8"
1971 17m 0000 00CF +SWT_NMSK SET (-SWT_MSK-1)&MSK8
1972 18m 0000 + ENDC
1973 19m 0000 + ENDC
1974 252i 0000 | DEF HME,B3 . halt monitor enable
1975 1m 0000 + IFC "",""
1976 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1977 3m 0000 0003 +.HME SET .B3
1978 4m 0000 + ENDC
1979 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
1980 6m 0000 0008 +_HME SET _B3
1981 7m 0000 + ENDC
1982 8m 0000 + ENDC
1983 9m 0000 + IFNC "",""
1984 10m 0000 +.HME SET .B3
1985 11m 0000 +HME_ SET _B3
1986 12m 0000 +HME_MSK SET (MSK)<<.B3
1987 13m 0000 + IFC "",""
1988 14m 0000 +HME_NMSK SET (-HME_MSK-1)&MSK16
1989 15m 0000 + ENDC
1990 16m 0000 + IFNC "",""
1991 17m 0000 +HME_NMSK SET (-HME_MSK-1)&
1992 18m 0000 + ENDC
1993 19m 0000 + ENDC
1994 253i 0000 | DEF BME,B2 . bus monitor external enable
1995 1m 0000 + IFC "",""
1996 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
1997 3m 0000 0002 +.BME SET .B2
1998 4m 0000 + ENDC
1999 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2000 6m 0000 0004 +_BME SET _B2
2001 7m 0000 + ENDC
2002 8m 0000 + ENDC
2003 9m 0000 + IFNC "",""
2004 10m 0000 +.BME SET .B2
2005 11m 0000 +BME_ SET _B2
2006 12m 0000 +BME_MSK SET (MSK)<<.B2
2007 13m 0000 + IFC "",""
2008 14m 0000 +BME_NMSK SET (-BME_MSK-1)&MSK16
2009 15m 0000 + ENDC
2010 16m 0000 + IFNC "",""
2011 17m 0000 +BME_NMSK SET (-BME_MSK-1)&
2012 18m 0000 + ENDC
2013 19m 0000 + ENDC
2014 254i 0000 | DEF BMT,B0,2,MSK8 . bus monitor timing (2 bits)
2015 1m 0000 + IFC "","2"
2016 2m 0000 + IFNE BIT$CODE&BIT$NUM
2017 3m 0000 +.BMT SET .B0
2018 4m 0000 + ENDC
2019 5m 0000 + IFNE BIT$CODE&BIT$VAL
2020 6m 0000 +_BMT SET _B0
2021 7m 0000 + ENDC
2022 8m 0000 + ENDC
2023 9m 0000 + IFNC "","2"
2024 10m 0000 0000 +.BMT SET .B0
2025 11m 0000 0001 +BMT_ SET _B0
2026 12m 0000 0003 +BMT_MSK SET (MSK2)<<.B0
2027 13m 0000 + IFC "","MSK8"
2028 14m 0000 +BMT_NMSK SET (-BMT_MSK-1)&MSK16
2029 15m 0000 + ENDC
2030 16m 0000 + IFNC "","MSK8"
2031 17m 0000 00FC +BMT_NMSK SET (-BMT_MSK-1)&MSK8
2032 18m 0000 + ENDC
2033 19m 0000 + ENDC
2034 255i 0000 |*-------------------------------------------------------------------*
2035 256i 0000 0022 |PICR EQU $022 Periodic Interrupt Control Register
2036 257i 0000 | DEF PIRQL,B8,3 . periodic int. request level (3 bits)
2037 1m 0000 + IFC "","3"
2038 2m 0000 + IFNE BIT$CODE&BIT$NUM
2039 3m 0000 +.PIRQL SET .B8
2040 4m 0000 + ENDC
2041 5m 0000 + IFNE BIT$CODE&BIT$VAL
2042 6m 0000 +_PIRQL SET _B8
2043 7m 0000 + ENDC
2044 8m 0000 + ENDC
2045 9m 0000 + IFNC "","3"
2046 10m 0000 0008 +.PIRQL SET .B8
2047 11m 0000 0100 +PIRQL_ SET _B8
2048 12m 0000 0700 +PIRQL_MSK SET (MSK3)<<.B8
2049 13m 0000 + IFC "",""
2050 14m 0000 F8FF +PIRQL_NMSK SET (-PIRQL_MSK-1)&MSK16
2051 15m 0000 + ENDC
2052 16m 0000 + IFNC "",""
2053 17m 0000 +PIRQL_NMSK SET (-PIRQL_MSK-1)&
2054 18m 0000 + ENDC
2055 19m 0000 + ENDC
2056 258i 0000 | DEF PIV,B0,8 . periodic interrupt vector (8 bits)
2057 1m 0000 + IFC "","8"
2058 2m 0000 + IFNE BIT$CODE&BIT$NUM
2059 3m 0000 +.PIV SET .B0
2060 4m 0000 + ENDC
2061 5m 0000 + IFNE BIT$CODE&BIT$VAL
2062 6m 0000 +_PIV SET _B0
2063 7m 0000 + ENDC
2064 8m 0000 + ENDC
2065 9m 0000 + IFNC "","8"
2066 10m 0000 0000 +.PIV SET .B0
2067 11m 0000 0001 +PIV_ SET _B0
2068 12m 0000 00FF +PIV_MSK SET (MSK8)<<.B0
2069 13m 0000 + IFC "",""
2070 14m 0000 FF00 +PIV_NMSK SET (-PIV_MSK-1)&MSK16
2071 15m 0000 + ENDC
2072 16m 0000 + IFNC "",""
2073 17m 0000 +PIV_NMSK SET (-PIV_MSK-1)&
2074 18m 0000 + ENDC
2075 19m 0000 + ENDC
2076 259i 0000 |*-------------------------------------------------------------------*
2077 260i 0000 0024 |PITR EQU $024 Periodic Interrupt Timing Register
2078 261i 0000 | DEF PTP,B8 . periodic timer prescaler control
2079 1m 0000 + IFC "",""
2080 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2081 3m 0000 0008 +.PTP SET .B8
2082 4m 0000 + ENDC
2083 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2084 6m 0000 0100 +_PTP SET _B8
2085 7m 0000 + ENDC
2086 8m 0000 + ENDC
2087 9m 0000 + IFNC "",""
2088 10m 0000 +.PTP SET .B8
2089 11m 0000 +PTP_ SET _B8
2090 12m 0000 +PTP_MSK SET (MSK)<<.B8
2091 13m 0000 + IFC "",""
2092 14m 0000 +PTP_NMSK SET (-PTP_MSK-1)&MSK16
2093 15m 0000 + ENDC
2094 16m 0000 + IFNC "",""
2095 17m 0000 +PTP_NMSK SET (-PTP_MSK-1)&
2096 18m 0000 + ENDC
2097 19m 0000 + ENDC
2098 262i 0000 | DEF PITM,B0,8 . periodic timer modulus (8 bits)
2099 1m 0000 + IFC "","8"
2100 2m 0000 + IFNE BIT$CODE&BIT$NUM
2101 3m 0000 +.PITM SET .B0
2102 4m 0000 + ENDC
2103 5m 0000 + IFNE BIT$CODE&BIT$VAL
2104 6m 0000 +_PITM SET _B0
2105 7m 0000 + ENDC
2106 8m 0000 + ENDC
2107 9m 0000 + IFNC "","8"
2108 10m 0000 0000 +.PITM SET .B0
2109 11m 0000 0001 +PITM_ SET _B0
2110 12m 0000 00FF +PITM_MSK SET (MSK8)<<.B0
2111 13m 0000 + IFC "",""
2112 14m 0000 FF00 +PITM_NMSK SET (-PITM_MSK-1)&MSK16
2113 15m 0000 + ENDC
2114 16m 0000 + IFNC "",""
2115 17m 0000 +PITM_NMSK SET (-PITM_MSK-1)&
2116 18m 0000 + ENDC
2117 19m 0000 + ENDC
2118 263i 0000 |*-------------------------------------------------------------------*
2119 264i 0000 |*UNUSED EQU $026 Unused position (BYTE)
2120 265i 0000 |*-------------------------------------------------------------------*
2121 266i 0000 0027 |SWSR EQU $027 Software Service Register (BYTE)
2122 267i 0000 |* NOTE: SWSR register always reads as zero (0)!
2123 268i 0000 | DEF SWSR,B0,8,MSK8 . software watchdog count (8 bits)
2124 1m 0000 + IFC "","8"
2125 2m 0000 + IFNE BIT$CODE&BIT$NUM
2126 3m 0000 +.SWSR SET .B0
2127 4m 0000 + ENDC
2128 5m 0000 + IFNE BIT$CODE&BIT$VAL
2129 6m 0000 +_SWSR SET _B0
2130 7m 0000 + ENDC
2131 8m 0000 + ENDC
2132 9m 0000 + IFNC "","8"
2133 10m 0000 0000 +.SWSR SET .B0
2134 11m 0000 0001 +SWSR_ SET _B0
2135 12m 0000 00FF +SWSR_MSK SET (MSK8)<<.B0
2136 13m 0000 + IFC "","MSK8"
2137 14m 0000 +SWSR_NMSK SET (-SWSR_MSK-1)&MSK16
2138 15m 0000 + ENDC
2139 16m 0000 + IFNC "","MSK8"
2140 17m 0000 0000 +SWSR_NMSK SET (-SWSR_MSK-1)&MSK8
2141 18m 0000 + ENDC
2142 19m 0000 + ENDC
2143 269i 0000 |*-------------------------------------------------------------------*
2144 270i 0000 |*UNUSED EQU $028 Unused position
2145 271i 0000 |*-------------------------------------------------------------------*
2146 272i 0000 0030 |TSTMSRA EQU $030 Test Module Master Shift Register A
2147 273i 0000 |*-------------------------------------------------------------------*
2148 274i 0000 0032 |TSTMSRB EQU $032 Test Module Master Shift Register B
2149 275i 0000 |*-------------------------------------------------------------------*
2150 276i 0000 0034 |TSTSC EQU $034 Test Module Shift Count
2151 277i 0000 |*-------------------------------------------------------------------*
2152 278i 0000 0036 |TSTRC EQU $036 Test Module Repetition Counter
2153 279i 0000 |*-------------------------------------------------------------------*
2154 280i 0000 0038 |CREG EQU $038 Test Module Control Register
2155 281i 0000 | DEF BUSY,B15 . busy status bit
2156 1m 0000 + IFC "",""
2157 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2158 3m 0000 000F +.BUSY SET .B15
2159 4m 0000 + ENDC
2160 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2161 6m 0000 8000 +_BUSY SET _B15
2162 7m 0000 + ENDC
2163 8m 0000 + ENDC
2164 9m 0000 + IFNC "",""
2165 10m 0000 +.BUSY SET .B15
2166 11m 0000 +BUSY_ SET _B15
2167 12m 0000 +BUSY_MSK SET (MSK)<<.B15
2168 13m 0000 + IFC "",""
2169 14m 0000 +BUSY_NMSK SET (-BUSY_MSK-1)&MSK16
2170 15m 0000 + ENDC
2171 16m 0000 + IFNC "",""
2172 17m 0000 +BUSY_NMSK SET (-BUSY_MSK-1)&
2173 18m 0000 + ENDC
2174 19m 0000 + ENDC
2175 282i 0000 |* NOTE: BUSY is not writable; read only!
2176 283i 0000 | DEF TMARM,B14 . test mode armed status bit
2177 1m 0000 + IFC "",""
2178 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2179 3m 0000 000E +.TMARM SET .B14
2180 4m 0000 + ENDC
2181 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2182 6m 0000 4000 +_TMARM SET _B14
2183 7m 0000 + ENDC
2184 8m 0000 + ENDC
2185 9m 0000 + IFNC "",""
2186 10m 0000 +.TMARM SET .B14
2187 11m 0000 +TMARM_ SET _B14
2188 12m 0000 +TMARM_MSK SET (MSK)<<.B14
2189 13m 0000 + IFC "",""
2190 14m 0000 +TMARM_NMSK SET (-TMARM_MSK-1)&MSK16
2191 15m 0000 + ENDC
2192 16m 0000 + IFNC "",""
2193 17m 0000 +TMARM_NMSK SET (-TMARM_MSK-1)&
2194 18m 0000 + ENDC
2195 19m 0000 + ENDC
2196 284i 0000 | DEF COMP,B13 . compare status bit
2197 1m 0000 + IFC "",""
2198 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2199 3m 0000 000D +.COMP SET .B13
2200 4m 0000 + ENDC
2201 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2202 6m 0000 2000 +_COMP SET _B13
2203 7m 0000 + ENDC
2204 8m 0000 + ENDC
2205 9m 0000 + IFNC "",""
2206 10m 0000 +.COMP SET .B13
2207 11m 0000 +COMP_ SET _B13
2208 12m 0000 +COMP_MSK SET (MSK)<<.B13
2209 13m 0000 + IFC "",""
2210 14m 0000 +COMP_NMSK SET (-COMP_MSK-1)&MSK16
2211 15m 0000 + ENDC
2212 16m 0000 + IFNC "",""
2213 17m 0000 +COMP_NMSK SET (-COMP_MSK-1)&
2214 18m 0000 + ENDC
2215 19m 0000 + ENDC
2216 285i 0000 | DEF IMBTST,B12 . intermodule bus test
2217 1m 0000 + IFC "",""
2218 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2219 3m 0000 000C +.IMBTST SET .B12
2220 4m 0000 + ENDC
2221 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2222 6m 0000 1000 +_IMBTST SET _B12
2223 7m 0000 + ENDC
2224 8m 0000 + ENDC
2225 9m 0000 + IFNC "",""
2226 10m 0000 +.IMBTST SET .B12
2227 11m 0000 +IMBTST_ SET _B12
2228 12m 0000 +IMBTST_MSK SET (MSK)<<.B12
2229 13m 0000 + IFC "",""
2230 14m 0000 +IMBTST_NMSK SET (-IMBTST_MSK-1)&MSK16
2231 15m 0000 + ENDC
2232 16m 0000 + IFNC "",""
2233 17m 0000 +IMBTST_NMSK SET (-IMBTST_MSK-1)&
2234 18m 0000 + ENDC
2235 19m 0000 + ENDC
2236 286i 0000 | DEF CPUTR,B11 . CPU test register
2237 1m 0000 + IFC "",""
2238 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2239 3m 0000 000B +.CPUTR SET .B11
2240 4m 0000 + ENDC
2241 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2242 6m 0000 0800 +_CPUTR SET _B11
2243 7m 0000 + ENDC
2244 8m 0000 + ENDC
2245 9m 0000 + IFNC "",""
2246 10m 0000 +.CPUTR SET .B11
2247 11m 0000 +CPUTR_ SET _B11
2248 12m 0000 +CPUTR_MSK SET (MSK)<<.B11
2249 13m 0000 + IFC "",""
2250 14m 0000 +CPUTR_NMSK SET (-CPUTR_MSK-1)&MSK16
2251 15m 0000 + ENDC
2252 16m 0000 + IFNC "",""
2253 17m 0000 +CPUTR_NMSK SET (-CPUTR_MSK-1)&
2254 18m 0000 + ENDC
2255 19m 0000 + ENDC
2256 287i 0000 | DEF QBIT,B10 . quotient bit
2257 1m 0000 + IFC "",""
2258 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2259 3m 0000 000A +.QBIT SET .B10
2260 4m 0000 + ENDC
2261 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2262 6m 0000 0400 +_QBIT SET _B10
2263 7m 0000 + ENDC
2264 8m 0000 + ENDC
2265 9m 0000 + IFNC "",""
2266 10m 0000 +.QBIT SET .B10
2267 11m 0000 +QBIT_ SET _B10
2268 12m 0000 +QBIT_MSK SET (MSK)<<.B10
2269 13m 0000 + IFC "",""
2270 14m 0000 +QBIT_NMSK SET (-QBIT_MSK-1)&MSK16
2271 15m 0000 + ENDC
2272 16m 0000 + IFNC "",""
2273 17m 0000 +QBIT_NMSK SET (-QBIT_MSK-1)&
2274 18m 0000 + ENDC
2275 19m 0000 + ENDC
2276 288i 0000 | DEF MUXEL,B9 . multiplexer select bit
2277 1m 0000 + IFC "",""
2278 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2279 3m 0000 0009 +.MUXEL SET .B9
2280 4m 0000 + ENDC
2281 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2282 6m 0000 0200 +_MUXEL SET _B9
2283 7m 0000 + ENDC
2284 8m 0000 + ENDC
2285 9m 0000 + IFNC "",""
2286 10m 0000 +.MUXEL SET .B9
2287 11m 0000 +MUXEL_ SET _B9
2288 12m 0000 +MUXEL_MSK SET (MSK)<<.B9
2289 13m 0000 + IFC "",""
2290 14m 0000 +MUXEL_NMSK SET (-MUXEL_MSK-1)&MSK16
2291 15m 0000 + ENDC
2292 16m 0000 + IFNC "",""
2293 17m 0000 +MUXEL_NMSK SET (-MUXEL_MSK-1)&
2294 18m 0000 + ENDC
2295 19m 0000 + ENDC
2296 289i 0000 | DEF ACUT,B4 . activate circuit under test
2297 1m 0000 + IFC "",""
2298 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2299 3m 0000 0004 +.ACUT SET .B4
2300 4m 0000 + ENDC
2301 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2302 6m 0000 0010 +_ACUT SET _B4
2303 7m 0000 + ENDC
2304 8m 0000 + ENDC
2305 9m 0000 + IFNC "",""
2306 10m 0000 +.ACUT SET .B4
2307 11m 0000 +ACUT_ SET _B4
2308 12m 0000 +ACUT_MSK SET (MSK)<<.B4
2309 13m 0000 + IFC "",""
2310 14m 0000 +ACUT_NMSK SET (-ACUT_MSK-1)&MSK16
2311 15m 0000 + ENDC
2312 16m 0000 + IFNC "",""
2313 17m 0000 +ACUT_NMSK SET (-ACUT_MSK-1)&
2314 18m 0000 + ENDC
2315 19m 0000 + ENDC
2316 290i 0000 |* NOTE: ACUT always reads as zero (0)!
2317 291i 0000 | DEF SCONT,B3 . start continuous operation
2318 1m 0000 + IFC "",""
2319 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2320 3m 0000 0003 +.SCONT SET .B3
2321 4m 0000 + ENDC
2322 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2323 6m 0000 0008 +_SCONT SET _B3
2324 7m 0000 + ENDC
2325 8m 0000 + ENDC
2326 9m 0000 + IFNC "",""
2327 10m 0000 +.SCONT SET .B3
2328 11m 0000 +SCONT_ SET _B3
2329 12m 0000 +SCONT_MSK SET (MSK)<<.B3
2330 13m 0000 + IFC "",""
2331 14m 0000 +SCONT_NMSK SET (-SCONT_MSK-1)&MSK16
2332 15m 0000 + ENDC
2333 16m 0000 + IFNC "",""
2334 17m 0000 +SCONT_NMSK SET (-SCONT_MSK-1)&
2335 18m 0000 + ENDC
2336 19m 0000 + ENDC
2337 292i 0000 | DEF SSHOP,B2 . start shifting operation
2338 1m 0000 + IFC "",""
2339 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2340 3m 0000 0002 +.SSHOP SET .B2
2341 4m 0000 + ENDC
2342 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2343 6m 0000 0004 +_SSHOP SET _B2
2344 7m 0000 + ENDC
2345 8m 0000 + ENDC
2346 9m 0000 + IFNC "",""
2347 10m 0000 +.SSHOP SET .B2
2348 11m 0000 +SSHOP_ SET _B2
2349 12m 0000 +SSHOP_MSK SET (MSK)<<.B2
2350 13m 0000 + IFC "",""
2351 14m 0000 +SSHOP_NMSK SET (-SSHOP_MSK-1)&MSK16
2352 15m 0000 + ENDC
2353 16m 0000 + IFNC "",""
2354 17m 0000 +SSHOP_NMSK SET (-SSHOP_MSK-1)&
2355 18m 0000 + ENDC
2356 19m 0000 + ENDC
2357 293i 0000 | DEF SATO,B1 . start automatic test operation
2358 1m 0000 + IFC "",""
2359 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2360 3m 0000 0001 +.SATO SET .B1
2361 4m 0000 + ENDC
2362 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2363 6m 0000 0002 +_SATO SET _B1
2364 7m 0000 + ENDC
2365 8m 0000 + ENDC
2366 9m 0000 + IFNC "",""
2367 10m 0000 +.SATO SET .B1
2368 11m 0000 +SATO_ SET _B1
2369 12m 0000 +SATO_MSK SET (MSK)<<.B1
2370 13m 0000 + IFC "",""
2371 14m 0000 +SATO_NMSK SET (-SATO_MSK-1)&MSK16
2372 15m 0000 + ENDC
2373 16m 0000 + IFNC "",""
2374 17m 0000 +SATO_NMSK SET (-SATO_MSK-1)&
2375 18m 0000 + ENDC
2376 19m 0000 + ENDC
2377 294i 0000 | DEF ETM,B0 . enter test mode
2378 1m 0000 + IFC "",""
2379 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2380 3m 0000 0000 +.ETM SET .B0
2381 4m 0000 + ENDC
2382 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2383 6m 0000 0001 +_ETM SET _B0
2384 7m 0000 + ENDC
2385 8m 0000 + ENDC
2386 9m 0000 + IFNC "",""
2387 10m 0000 +.ETM SET .B0
2388 11m 0000 +ETM_ SET _B0
2389 12m 0000 +ETM_MSK SET (MSK)<<.B0
2390 13m 0000 + IFC "",""
2391 14m 0000 +ETM_NMSK SET (-ETM_MSK-1)&MSK16
2392 15m 0000 + ENDC
2393 16m 0000 + IFNC "",""
2394 17m 0000 +ETM_NMSK SET (-ETM_MSK-1)&
2395 18m 0000 + ENDC
2396 19m 0000 + ENDC
2397 295i 0000 |* NOTE: ETM is a WRITE-ONCE bit!
2398 296i 0000 |*-------------------------------------------------------------------*
2399 297i 0000 003A |DREG EQU $03A Test Module Distributed Register
2400 298i 0000 | DEF WAIT,B8,3 . wait counter preset (3 bits)
2401 1m 0000 + IFC "","3"
2402 2m 0000 + IFNE BIT$CODE&BIT$NUM
2403 3m 0000 +.WAIT SET .B8
2404 4m 0000 + ENDC
2405 5m 0000 + IFNE BIT$CODE&BIT$VAL
2406 6m 0000 +_WAIT SET _B8
2407 7m 0000 + ENDC
2408 8m 0000 + ENDC
2409 9m 0000 + IFNC "","3"
2410 10m 0000 0008 +.WAIT SET .B8
2411 11m 0000 0100 +WAIT_ SET _B8
2412 12m 0000 0700 +WAIT_MSK SET (MSK3)<<.B8
2413 13m 0000 + IFC "",""
2414 14m 0000 F8FF +WAIT_NMSK SET (-WAIT_MSK-1)&MSK16
2415 15m 0000 + ENDC
2416 16m 0000 + IFNC "",""
2417 17m 0000 +WAIT_NMSK SET (-WAIT_MSK-1)&
2418 18m 0000 + ENDC
2419 19m 0000 + ENDC
2420 299i 0000 | DEF MSRA18,B7 . master shift reg. A bit 18
2421 1m 0000 + IFC "",""
2422 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2423 3m 0000 0007 +.MSRA18 SET .B7
2424 4m 0000 + ENDC
2425 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2426 6m 0000 0080 +_MSRA18 SET _B7
2427 7m 0000 + ENDC
2428 8m 0000 + ENDC
2429 9m 0000 + IFNC "",""
2430 10m 0000 +.MSRA18 SET .B7
2431 11m 0000 +MSRA18_ SET _B7
2432 12m 0000 +MSRA18_MSK SET (MSK)<<.B7
2433 13m 0000 + IFC "",""
2434 14m 0000 +MSRA18_NMSK SET (-MSRA18_MSK-1)&MSK16
2435 15m 0000 + ENDC
2436 16m 0000 + IFNC "",""
2437 17m 0000 +MSRA18_NMSK SET (-MSRA18_MSK-1)&
2438 18m 0000 + ENDC
2439 19m 0000 + ENDC
2440 300i 0000 | DEF MSRA17,B6 . master shift reg. A bit 17
2441 1m 0000 + IFC "",""
2442 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2443 3m 0000 0006 +.MSRA17 SET .B6
2444 4m 0000 + ENDC
2445 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2446 6m 0000 0040 +_MSRA17 SET _B6
2447 7m 0000 + ENDC
2448 8m 0000 + ENDC
2449 9m 0000 + IFNC "",""
2450 10m 0000 +.MSRA17 SET .B6
2451 11m 0000 +MSRA17_ SET _B6
2452 12m 0000 +MSRA17_MSK SET (MSK)<<.B6
2453 13m 0000 + IFC "",""
2454 14m 0000 +MSRA17_NMSK SET (-MSRA17_MSK-1)&MSK16
2455 15m 0000 + ENDC
2456 16m 0000 + IFNC "",""
2457 17m 0000 +MSRA17_NMSK SET (-MSRA17_MSK-1)&
2458 18m 0000 + ENDC
2459 19m 0000 + ENDC
2460 301i 0000 | DEF MSRA16,B5 . master shift reg. A bit 16
2461 1m 0000 + IFC "",""
2462 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2463 3m 0000 0005 +.MSRA16 SET .B5
2464 4m 0000 + ENDC
2465 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2466 6m 0000 0020 +_MSRA16 SET _B5
2467 7m 0000 + ENDC
2468 8m 0000 + ENDC
2469 9m 0000 + IFNC "",""
2470 10m 0000 +.MSRA16 SET .B5
2471 11m 0000 +MSRA16_ SET _B5
2472 12m 0000 +MSRA16_MSK SET (MSK)<<.B5
2473 13m 0000 + IFC "",""
2474 14m 0000 +MSRA16_NMSK SET (-MSRA16_MSK-1)&MSK16
2475 15m 0000 + ENDC
2476 16m 0000 + IFNC "",""
2477 17m 0000 +MSRA16_NMSK SET (-MSRA16_MSK-1)&
2478 18m 0000 + ENDC
2479 19m 0000 + ENDC
2480 302i 0000 | DEF MSRA,B5,3 . master shift reg. A bits 16-18 (3 bits)
2481 1m 0000 + IFC "","3"
2482 2m 0000 + IFNE BIT$CODE&BIT$NUM
2483 3m 0000 +.MSRA SET .B5
2484 4m 0000 + ENDC
2485 5m 0000 + IFNE BIT$CODE&BIT$VAL
2486 6m 0000 +_MSRA SET _B5
2487 7m 0000 + ENDC
2488 8m 0000 + ENDC
2489 9m 0000 + IFNC "","3"
2490 10m 0000 0005 +.MSRA SET .B5
2491 11m 0000 0020 +MSRA_ SET _B5
2492 12m 0000 00E0 +MSRA_MSK SET (MSK3)<<.B5
2493 13m 0000 + IFC "",""
2494 14m 0000 FF1F +MSRA_NMSK SET (-MSRA_MSK-1)&MSK16
2495 15m 0000 + ENDC
2496 16m 0000 + IFNC "",""
2497 17m 0000 +MSRA_NMSK SET (-MSRA_MSK-1)&
2498 18m 0000 + ENDC
2499 19m 0000 + ENDC
2500 303i 0000 | DEF MSRAC,B4 . master shift reg. A configuration
2501 1m 0000 + IFC "",""
2502 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2503 3m 0000 0004 +.MSRAC SET .B4
2504 4m 0000 + ENDC
2505 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2506 6m 0000 0010 +_MSRAC SET _B4
2507 7m 0000 + ENDC
2508 8m 0000 + ENDC
2509 9m 0000 + IFNC "",""
2510 10m 0000 +.MSRAC SET .B4
2511 11m 0000 +MSRAC_ SET _B4
2512 12m 0000 +MSRAC_MSK SET (MSK)<<.B4
2513 13m 0000 + IFC "",""
2514 14m 0000 +MSRAC_NMSK SET (-MSRAC_MSK-1)&MSK16
2515 15m 0000 + ENDC
2516 16m 0000 + IFNC "",""
2517 17m 0000 +MSRAC_NMSK SET (-MSRAC_MSK-1)&
2518 18m 0000 + ENDC
2519 19m 0000 + ENDC
2520 304i 0000 | DEF MSRB18,B3 . master shift reg. B bit 18
2521 1m 0000 + IFC "",""
2522 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2523 3m 0000 0003 +.MSRB18 SET .B3
2524 4m 0000 + ENDC
2525 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2526 6m 0000 0008 +_MSRB18 SET _B3
2527 7m 0000 + ENDC
2528 8m 0000 + ENDC
2529 9m 0000 + IFNC "",""
2530 10m 0000 +.MSRB18 SET .B3
2531 11m 0000 +MSRB18_ SET _B3
2532 12m 0000 +MSRB18_MSK SET (MSK)<<.B3
2533 13m 0000 + IFC "",""
2534 14m 0000 +MSRB18_NMSK SET (-MSRB18_MSK-1)&MSK16
2535 15m 0000 + ENDC
2536 16m 0000 + IFNC "",""
2537 17m 0000 +MSRB18_NMSK SET (-MSRB18_MSK-1)&
2538 18m 0000 + ENDC
2539 19m 0000 + ENDC
2540 305i 0000 | DEF MSRB17,B2 . master shift reg. B bit 17
2541 1m 0000 + IFC "",""
2542 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2543 3m 0000 0002 +.MSRB17 SET .B2
2544 4m 0000 + ENDC
2545 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2546 6m 0000 0004 +_MSRB17 SET _B2
2547 7m 0000 + ENDC
2548 8m 0000 + ENDC
2549 9m 0000 + IFNC "",""
2550 10m 0000 +.MSRB17 SET .B2
2551 11m 0000 +MSRB17_ SET _B2
2552 12m 0000 +MSRB17_MSK SET (MSK)<<.B2
2553 13m 0000 + IFC "",""
2554 14m 0000 +MSRB17_NMSK SET (-MSRB17_MSK-1)&MSK16
2555 15m 0000 + ENDC
2556 16m 0000 + IFNC "",""
2557 17m 0000 +MSRB17_NMSK SET (-MSRB17_MSK-1)&
2558 18m 0000 + ENDC
2559 19m 0000 + ENDC
2560 306i 0000 | DEF MSRB16,B1 . master shift reg. B bit 16
2561 1m 0000 + IFC "",""
2562 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2563 3m 0000 0001 +.MSRB16 SET .B1
2564 4m 0000 + ENDC
2565 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2566 6m 0000 0002 +_MSRB16 SET _B1
2567 7m 0000 + ENDC
2568 8m 0000 + ENDC
2569 9m 0000 + IFNC "",""
2570 10m 0000 +.MSRB16 SET .B1
2571 11m 0000 +MSRB16_ SET _B1
2572 12m 0000 +MSRB16_MSK SET (MSK)<<.B1
2573 13m 0000 + IFC "",""
2574 14m 0000 +MSRB16_NMSK SET (-MSRB16_MSK-1)&MSK16
2575 15m 0000 + ENDC
2576 16m 0000 + IFNC "",""
2577 17m 0000 +MSRB16_NMSK SET (-MSRB16_MSK-1)&
2578 18m 0000 + ENDC
2579 19m 0000 + ENDC
2580 307i 0000 | DEF MSRB,B1,3 . master shift reg. B bits 16-18 (3 bits)
2581 1m 0000 + IFC "","3"
2582 2m 0000 + IFNE BIT$CODE&BIT$NUM
2583 3m 0000 +.MSRB SET .B1
2584 4m 0000 + ENDC
2585 5m 0000 + IFNE BIT$CODE&BIT$VAL
2586 6m 0000 +_MSRB SET _B1
2587 7m 0000 + ENDC
2588 8m 0000 + ENDC
2589 9m 0000 + IFNC "","3"
2590 10m 0000 0001 +.MSRB SET .B1
2591 11m 0000 0002 +MSRB_ SET _B1
2592 12m 0000 000E +MSRB_MSK SET (MSK3)<<.B1
2593 13m 0000 + IFC "",""
2594 14m 0000 FFF1 +MSRB_NMSK SET (-MSRB_MSK-1)&MSK16
2595 15m 0000 + ENDC
2596 16m 0000 + IFNC "",""
2597 17m 0000 +MSRB_NMSK SET (-MSRB_MSK-1)&
2598 18m 0000 + ENDC
2599 19m 0000 + ENDC
2600 308i 0000 | DEF MSRBC,B0 . master shift reg. B configuration
2601 1m 0000 + IFC "",""
2602 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2603 3m 0000 0000 +.MSRBC SET .B0
2604 4m 0000 + ENDC
2605 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2606 6m 0000 0001 +_MSRBC SET _B0
2607 7m 0000 + ENDC
2608 8m 0000 + ENDC
2609 9m 0000 + IFNC "",""
2610 10m 0000 +.MSRBC SET .B0
2611 11m 0000 +MSRBC_ SET _B0
2612 12m 0000 +MSRBC_MSK SET (MSK)<<.B0
2613 13m 0000 + IFC "",""
2614 14m 0000 +MSRBC_NMSK SET (-MSRBC_MSK-1)&MSK16
2615 15m 0000 + ENDC
2616 16m 0000 + IFNC "",""
2617 17m 0000 +MSRBC_NMSK SET (-MSRBC_MSK-1)&
2618 18m 0000 + ENDC
2619 19m 0000 + ENDC
2620 309i 0000 |*-- Wait Counter Values --*
2621 310i 0000 0000 |WAIT$2 EQU 0 Delay 2 system clock cycles
2622 311i 0000 0001 |WAIT$4 EQU 1 Delay 4 system clock cycles
2623 312i 0000 0002 |WAIT$6 EQU 2 Delay 6 system clock cycles
2624 313i 0000 0003 |WAIT$8 EQU 3 Delay 8 system clock cycles
2625 314i 0000 0004 |WAIT$10 EQU 4 Delay 10 system clock cycles
2626 315i 0000 0005 |WAIT$12 EQU 5 Delay 12 system clock cycles
2627 316i 0000 0006 |WAIT$14 EQU 6 Delay 14 system clock cycles
2628 317i 0000 0007 |WAIT$16 EQU 7 Delay 16 system clock cycles
2629 318i 0000 |*-------------------------------------------------------------------*
2630 319i 0000 |*UNUSED EQU $03C Unused position
2631 320i 0000 |*-------------------------------------------------------------------*
2632 321i 0000 |*UNUSED EQU $03E Unused position
2633 322i 0000 |*-------------------------------------------------------------------*
2634 323i 0000 |*UNUSED EQU $040 Unused position (BYTE)
2635 324i 0000 |*-------------------------------------------------------------------*
2636 325i 0000 0041 |PORTC EQU $041 Port C Data Register (BYTE)
2637 326i 0000 | DEF PC7,B7 . port C data bit 7
2638 1m 0000 + IFC "",""
2639 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2640 3m 0000 0007 +.PC7 SET .B7
2641 4m 0000 + ENDC
2642 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2643 6m 0000 0080 +_PC7 SET _B7
2644 7m 0000 + ENDC
2645 8m 0000 + ENDC
2646 9m 0000 + IFNC "",""
2647 10m 0000 +.PC7 SET .B7
2648 11m 0000 +PC7_ SET _B7
2649 12m 0000 +PC7_MSK SET (MSK)<<.B7
2650 13m 0000 + IFC "",""
2651 14m 0000 +PC7_NMSK SET (-PC7_MSK-1)&MSK16
2652 15m 0000 + ENDC
2653 16m 0000 + IFNC "",""
2654 17m 0000 +PC7_NMSK SET (-PC7_MSK-1)&
2655 18m 0000 + ENDC
2656 19m 0000 + ENDC
2657 327i 0000 | DEF PC6,B6 . port C data bit 6
2658 1m 0000 + IFC "",""
2659 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2660 3m 0000 0006 +.PC6 SET .B6
2661 4m 0000 + ENDC
2662 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2663 6m 0000 0040 +_PC6 SET _B6
2664 7m 0000 + ENDC
2665 8m 0000 + ENDC
2666 9m 0000 + IFNC "",""
2667 10m 0000 +.PC6 SET .B6
2668 11m 0000 +PC6_ SET _B6
2669 12m 0000 +PC6_MSK SET (MSK)<<.B6
2670 13m 0000 + IFC "",""
2671 14m 0000 +PC6_NMSK SET (-PC6_MSK-1)&MSK16
2672 15m 0000 + ENDC
2673 16m 0000 + IFNC "",""
2674 17m 0000 +PC6_NMSK SET (-PC6_MSK-1)&
2675 18m 0000 + ENDC
2676 19m 0000 + ENDC
2677 328i 0000 | DEF PC5,B5 . port C data bit 5
2678 1m 0000 + IFC "",""
2679 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2680 3m 0000 0005 +.PC5 SET .B5
2681 4m 0000 + ENDC
2682 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2683 6m 0000 0020 +_PC5 SET _B5
2684 7m 0000 + ENDC
2685 8m 0000 + ENDC
2686 9m 0000 + IFNC "",""
2687 10m 0000 +.PC5 SET .B5
2688 11m 0000 +PC5_ SET _B5
2689 12m 0000 +PC5_MSK SET (MSK)<<.B5
2690 13m 0000 + IFC "",""
2691 14m 0000 +PC5_NMSK SET (-PC5_MSK-1)&MSK16
2692 15m 0000 + ENDC
2693 16m 0000 + IFNC "",""
2694 17m 0000 +PC5_NMSK SET (-PC5_MSK-1)&
2695 18m 0000 + ENDC
2696 19m 0000 + ENDC
2697 329i 0000 | DEF PC4,B4 . port C data bit 4
2698 1m 0000 + IFC "",""
2699 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2700 3m 0000 0004 +.PC4 SET .B4
2701 4m 0000 + ENDC
2702 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2703 6m 0000 0010 +_PC4 SET _B4
2704 7m 0000 + ENDC
2705 8m 0000 + ENDC
2706 9m 0000 + IFNC "",""
2707 10m 0000 +.PC4 SET .B4
2708 11m 0000 +PC4_ SET _B4
2709 12m 0000 +PC4_MSK SET (MSK)<<.B4
2710 13m 0000 + IFC "",""
2711 14m 0000 +PC4_NMSK SET (-PC4_MSK-1)&MSK16
2712 15m 0000 + ENDC
2713 16m 0000 + IFNC "",""
2714 17m 0000 +PC4_NMSK SET (-PC4_MSK-1)&
2715 18m 0000 + ENDC
2716 19m 0000 + ENDC
2717 330i 0000 | DEF PC3,B3 . port C data bit 3
2718 1m 0000 + IFC "",""
2719 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2720 3m 0000 0003 +.PC3 SET .B3
2721 4m 0000 + ENDC
2722 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2723 6m 0000 0008 +_PC3 SET _B3
2724 7m 0000 + ENDC
2725 8m 0000 + ENDC
2726 9m 0000 + IFNC "",""
2727 10m 0000 +.PC3 SET .B3
2728 11m 0000 +PC3_ SET _B3
2729 12m 0000 +PC3_MSK SET (MSK)<<.B3
2730 13m 0000 + IFC "",""
2731 14m 0000 +PC3_NMSK SET (-PC3_MSK-1)&MSK16
2732 15m 0000 + ENDC
2733 16m 0000 + IFNC "",""
2734 17m 0000 +PC3_NMSK SET (-PC3_MSK-1)&
2735 18m 0000 + ENDC
2736 19m 0000 + ENDC
2737 331i 0000 | DEF PC2,B2 . port C data bit 2
2738 1m 0000 + IFC "",""
2739 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2740 3m 0000 0002 +.PC2 SET .B2
2741 4m 0000 + ENDC
2742 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2743 6m 0000 0004 +_PC2 SET _B2
2744 7m 0000 + ENDC
2745 8m 0000 + ENDC
2746 9m 0000 + IFNC "",""
2747 10m 0000 +.PC2 SET .B2
2748 11m 0000 +PC2_ SET _B2
2749 12m 0000 +PC2_MSK SET (MSK)<<.B2
2750 13m 0000 + IFC "",""
2751 14m 0000 +PC2_NMSK SET (-PC2_MSK-1)&MSK16
2752 15m 0000 + ENDC
2753 16m 0000 + IFNC "",""
2754 17m 0000 +PC2_NMSK SET (-PC2_MSK-1)&
2755 18m 0000 + ENDC
2756 19m 0000 + ENDC
2757 332i 0000 | DEF PC1,B1 . port C data bit 1
2758 1m 0000 + IFC "",""
2759 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2760 3m 0000 0001 +.PC1 SET .B1
2761 4m 0000 + ENDC
2762 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2763 6m 0000 0002 +_PC1 SET _B1
2764 7m 0000 + ENDC
2765 8m 0000 + ENDC
2766 9m 0000 + IFNC "",""
2767 10m 0000 +.PC1 SET .B1
2768 11m 0000 +PC1_ SET _B1
2769 12m 0000 +PC1_MSK SET (MSK)<<.B1
2770 13m 0000 + IFC "",""
2771 14m 0000 +PC1_NMSK SET (-PC1_MSK-1)&MSK16
2772 15m 0000 + ENDC
2773 16m 0000 + IFNC "",""
2774 17m 0000 +PC1_NMSK SET (-PC1_MSK-1)&
2775 18m 0000 + ENDC
2776 19m 0000 + ENDC
2777 333i 0000 | DEF PC0,B0 . port C data bit 0
2778 1m 0000 + IFC "",""
2779 2m 0000 0001 + IFNE BIT$CODE&BIT$NUM
2780 3m 0000 0000 +.PC0 SET .B0
2781 4m 0000 + ENDC
2782 5m 0000 0002 + IFNE BIT$CODE&BIT$VAL
2783 6m 0000 0001 +_PC0 SET _B0
2784 7m 0000 + ENDC
2785 8m 0000 + ENDC
2786 9m 0000 + IFNC "",""
2787 10m 0000 +.PC0 SET .B0
2788 11m 0000 +PC0_ SET _B0
2789 12m 0000 +PC0_MSK SET (MSK)<<.B0
2790 13m 0000 + IFC "",""
2791 14m 0000 +PC0_NMSK SET (-PC0_MSK-1)&MSK16
2792 15m 0000 + ENDC
2793 16m 0000 + IFNC "",""
2794 17m 0000 +PC0_NMSK SET (-PC0_MSK-1)&
2795 18m 0000 + ENDC
2796 19m 0000 + ENDC
2797 334i 0000 |*-------------------------------------------------------------------*
2798 335i 0000 |*UNUSED EQU $042 Unused position
2799 336i 0000 |*-------------------------------------------------------------------*
2800 337i 0000 0044 |CSPAR0 EQU $044 Chip Select Pin Assignment Register 0
2801 338i 0000 |*-------------------------------------------------------------------*
2802 339i 0000 0046 |CSPAR1 EQU $046 Chip Select Pin Assignment Register 1
2803 340i 0000 |*-------------------------------------------------------------------*
2804 341i 0000 0048 |CSBARBT EQU $048 Chip Select Base Address Register Boot
2805 342i 0000 |* NOTE: For all CSBARxx registers,
2806 343i 0000 |* BITS 15-3= base address field (A23-A11)
2807 344i 0000 |* BITS 2-0 = block size field
2808 345i 0000 |* See "Chip Select Equates for CSORxx, CSBARxx:" below.
2809 346i 0000 |*-------------------------------------------------------------------*
2810 347i 0000 004A |CSORBT EQU $04A Chip Select Option Register Boot
2811 348i 0000 |* NOTE: For all CSORxx registers,
2812 349i 0000 |* BIT 15 = aysnc/sync mode (MODE)
2813 350i 0000 |* BITS 14-13= upper/lower byte option (BYTE)
2814 351i 0000 |* BITS 12-11= read/write (R/W)
2815 352i 0000 |* BIT 10 = address/data strobe (STRB)
2816 353i 0000 |* BITS 9-6 = data strobe acknowledge (DSACK)
2817 354i 0000 |* BITS 5-4 = address space (SPACE)
2818 355i 0000 |* BITS 3-1 = interrupt priority level (IPL)
2819 356i 0000 |* BIT 0 = autovector enable (AVEC)
2820 357i 0000 |* See "Chip Select Equates for CSORxx, CSBARxx:" below.
2821 358i 0000 |*-------------------------------------------------------------------*
2822 359i 0000 004C |CSBAR0 EQU $04C Chip Select Base Address Register 0
2823 360i 0000 |*-------------------------------------------------------------------*
2824 361i 0000 004E |CSOR0 EQU $04E Chip Select Option Register 0
2825 362i 0000 |*-------------------------------------------------------------------*
2826 363i 0000 0050 |CSBAR1 EQU $050 Chip Select Base Address Register 1
2827 364i 0000 |*-------------------------------------------------------------------*
2828 365i 0000 0052 |CSOR1 EQU $052 Chip Select Option Register 1
2829 366i 0000 |*-------------------------------------------------------------------*
2830 367i 0000 0054 |CSBAR2 EQU $054 Chip Select Base Address Register 2
2831 368i 0000 |*-------------------------------------------------------------------*
2832 369i 0000 0056 |CSOR2 EQU $056 Chip Select Option Register 2
2833 370i 0000 |*-------------------------------------------------------------------*
2834 371i 0000 0058 |CSBAR3 EQU $058 Chip Select Base Address Register 3
2835 372i 0000 |*-------------------------------------------------------------------*
2836 373i 0000 005A |CSOR3 EQU $05A Chip Select Option Register 3
2837 374i 0000 |*-------------------------------------------------------------------*
2838 375i 0000 005C |CSBAR4 EQU $05C Chip Select Base Address Register 4
2839 376i 0000 |*-------------------------------------------------------------------*
2840 377i 0000 005E |CSOR4 EQU $05E Chip Select Option Register 4
2841 378i 0000 |*-------------------------------------------------------------------*
2842 379i 0000 0060 |CSBAR5 EQU $060 Chip Select Base Address Register 5
2843 380i 0000 |*-------------------------------------------------------------------*
2844 381i 0000 0062 |CSOR5 EQU $062 Chip Select Option Register 5
2845 382i 0000 |*-------------------------------------------------------------------*
2846 383i 0000 0064 |CSBAR6 EQU $064 Chip Select Base Address Register 6
2847 384i 0000 |*-------------------------------------------------------------------*
2848 385i 0000 0066 |CSOR6 EQU $066 Chip Select Option Register 6
2849 386i 0000 |*-------------------------------------------------------------------*
2850 387i 0000 0068 |CSBAR7 EQU $068 Chip Select Base Address Register 7
2851 388i 0000 |*-------------------------------------------------------------------*
2852 389i 0000 006A |CSOR7 EQU $06A Chip Select Option Register 7
2853 390i 0000 |*-------------------------------------------------------------------*
2854 391i 0000 006C |CSBAR8 EQU $06C Chip Select Base Address Register 8
2855 392i 0000 |*-------------------------------------------------------------------*
2856 393i 0000 006E |CSOR8 EQU $06E Chip Select Option Register 8
2857 394i 0000 |*-------------------------------------------------------------------*
2858 395i 0000 0070 |CSBAR9 EQU $070 Chip Select Base Address Register 9
2859 396i 0000 |*-------------------------------------------------------------------*
2860 397i 0000 0072 |CSOR9 EQU $072 Chip Select Option Register 9
2861 398i 0000 |*-------------------------------------------------------------------*
2862 399i 0000 0074 |CSBAR10 EQU $074 Chip Select Base Address Register 10
2863 400i 0000 |*-------------------------------------------------------------------*
2864 401i 0000 0076 |CSOR10 EQU $076 Chip Select Option Register 10
2865 402i 0000 |*-------------------------------------------------------------------*
2866 403i 0000 |*UNUSED EQU $078 Unused position
2867 404i 0000 |*-------------------------------------------------------------------*
2868 405i 0000 |*UNUSED EQU $07A Unused position
2869 406i 0000 |*-------------------------------------------------------------------*
2870 407i 0000 |*UNUSED EQU $07C Unused position
2871 408i 0000 |*-------------------------------------------------------------------*
2872 409i 0000 |*UNUSED EQU $07E Unused position
2873 410i 0000 |*********************************************************************
2874 411i 0000 |
2875 412i 0000 |*
2876 413i 0000 |* Chip Select Equates for CSORxx, CSBARxx:
2877 414i 0000 |*
2878 415i 0000 0000 |CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
2879 416i 0000 0000 |CSOR_XX EQU $0000 Reset (unused) value for CSORn
2880 417i 0000 |*
2881 418i 0000 0000 |B2K EQU 0 2K block size
2882 419i 0000 0001 |B8K EQU 1 8K block size
2883 420i 0000 0002 |B16K EQU 2 16K block size
2884 421i 0000 0003 |B64K EQU 3 64K block size
2885 422i 0000 0004 |B128K EQU 4 128K block size
2886 423i 0000 0005 |B256K EQU 5 256K block size
2887 424i 0000 0006 |B512K EQU 6 512K block size
2888 425i 0000 0007 |B1M EQU 7 1MB block size
2889 426i 0000 0000 |ASYNC EQU $0000 Asynchronous mode
2890 427i 0000 8000 |SYNC EQU $8000 Synchronous mode
2891 428i 0000 4000 |CS_UPPB EQU 2*$2000 Upper byte
2892 429i 0000 2000 |CS_LOWB EQU 1*$2000 Lower byte
2893 430i 0000 6000 |CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
2894 431i 0000 0800 |CS_R EQU 1*$800 Read
2895 432i 0000 1000 |CS_W EQU 2*$800 Write
2896 433i 0000 1800 |CS_RW EQU 3*$800 Read or write
2897 434i 0000 0000 |CS_AS EQU 0*$400 Address Strobe (AS*)
2898 435i 0000 0400 |CS_DS EQU 1*$400 Data Strobe (DS*)
2899 436i 0000 000E |CS_FAST EQU 14 Fast termination DSACK*
2900 437i 0000 000F |CS_EXT EQU 15 External termination DSACK*
2901 438i 0000 0040 |CS_WAIT EQU 1*$40 Wait cycles for DSACK*
2902 439i 0000 0000 |CS_CSP EQU 0*$10 CPU space
2903 440i 0000 0010 |CS_USP EQU 1*$10 User space
2904 441i 0000 0020 |CS_SSP EQU 2*$10 Supervisor space
2905 442i 0000 0030 |CS_SUSP EQU 3*$10 Supervisor/User space
2906 443i 0000 0002 |CS_LVL EQU 1*$2 Interrupt priority level
2907 444i 0000 0001 |CS_AVEC EQU 1 Autovector enable
2908 445i 0000 |*********************************************************************
2909 8 0000 |
2910 9 0000 | END
2910 lines assembled
symbol table:
symbol name attrib. section value
----------- ------- ------- -----
REG$ abs. 0xfffff000
310 @5
BIT$NUM abs. 0x1
2779 2759 2739 2719 2699 2679 2659 2639 2602 2562
2542 2522 2502 2462 2442 2422 2379 2359 2339 2319
2298 2278 2258 2238 2218 2198 2178 2157 2080 1996
1976 1936 1916 1891 1871 1851 1831 1811 1791 1771
1751 1727 1707 1687 1667 1647 1627 1607 1587 1559
1539 1519 1499 1479 1459 1439 1419 1395 1375 1355
1335 1315 1295 1275 1255 1231 1211 1191 1171 1151
1131 1111 1091 1063 1043 1023 1003 983 963 943
923 890 870 850 830 810 790 770 745 725
705 685 665 645 605 585 438 418 378 358
338 318 59 @57
BIT$VAL abs. 0x2
2782 2762 2742 2722 2702 2682 2662 2642 2605 2565
2545 2525 2505 2465 2445 2425 2382 2362 2342 2322
2301 2281 2261 2241 2221 2201 2181 2160 2083 1999
1979 1939 1919 1894 1874 1854 1834 1814 1794 1774
1754 1730 1710 1690 1670 1650 1630 1610 1590 1562
1542 1522 1502 1482 1462 1442 1422 1398 1378 1358
1338 1318 1298 1278 1258 1234 1214 1194 1174 1154
1134 1114 1094 1066 1046 1026 1006 986 966 946
926 893 873 853 833 813 793 773 748 728
708 688 668 648 608 588 441 421 381 361
341 321 59 @58
BIT$BOTH abs. 0x3
61 @59
BIT$CODE abs. 0x3
2782 2779 2762 2759 2742 2739 2722 2719 2702 2699
2682 2679 2662 2659 2642 2639 2605 2602 2565 2562
2545 2542 2525 2522 2505 2502 2465 2462 2445 2442
2425 2422 2382 2379 2362 2359 2342 2339 2322 2319
2301 2298 2281 2278 2261 2258 2241 2238 2221 2218
2201 2198 2181 2178 2160 2157 2083 2080 1999 1996
1979 1976 1939 1936 1919 1916 1894 1891 1874 1871
1854 1851 1834 1831 1814 1811 1794 1791 1774 1771
1754 1751 1730 1727 1710 1707 1690 1687 1670 1667
1650 1647 1630 1627 1610 1607 1590 1587 1562 1559
1542 1539 1522 1519 1502 1499 1482 1479 1462 1459
1442 1439 1422 1419 1398 1395 1378 1375 1358 1355
1338 1335 1318 1315 1298 1295 1278 1275 1258 1255
1234 1231 1214 1211 1194 1191 1174 1171 1154 1151
1134 1131 1114 1111 1094 1091 1066 1063 1046 1043
1026 1023 1006 1003 986 983 966 963 946 943
926 923 893 890 873 870 853 850 833 830
813 810 793 790 773 770 748 745 728 725
708 705 688 685 668 665 648 645 608 605
588 585 441 438 421 418 381 378 361 358
341 338 321 318 @61
.B15 abs. 0xf
2158 586 319 87 @67
.B14 abs. 0xe
2179 606 339 88 @68
.B13 abs. 0xd
2199 359 89 @69
.B12 abs. 0xc
2219 90 @70
.B11 abs. 0xb
2239 379 91 @71
.B10 abs. 0xa
2259 491 489 92 @72
.B9 abs. 0x9
2279 93 @73
.B8 abs. 0x8
2412 2410 2081 2048 2046 635 633 408 406 94
@74
.B7 abs. 0x7
2640 2423 1917 1752 1588 1420 1256 1092 924 771
646 419 95 @75
.B6 abs. 0x6
2660 2443 1937 1772 1608 1440 1276 1112 944 791
511 509 439 96 @76
.B5 abs. 0x5
2680 2492 2490 2463 1792 1628 1460 1296 1132 964
811 97 @77
.B4 abs. 0x4
2700 2503 2299 1966 1964 1812 1648 1480 1316 1152
984 831 666 532 530 98 @78
.B3 abs. 0x3
2720 2523 2320 1977 1832 1668 1500 1336 1172 1004
686 99 @79
.B2 abs. 0x2
2740 2543 2340 1997 1852 1688 1520 1356 1192 1024
851 706 552 550 100 @80
.B1 abs. 0x1
2760 2592 2590 2563 2360 1872 1708 1540 1376 1212
1044 871 726 101 @81
.B0 abs. 0x0
2780 2603 2380 2135 2133 2110 2108 2068 2066 2026
2024 1892 1728 1560 1396 1232 1064 891 746 572
570 469 467 102 @82
_B15 abs. 0x8000
2161 589 322 @87
_B14 abs. 0x4000
2182 609 342 @88
_B13 abs. 0x2000
2202 362 @89
_B12 abs. 0x1000
2222 @90
_B11 abs. 0x800
2242 382 @91
_B10 abs. 0x400
2262 490 @92
_B9 abs. 0x200
2282 @93
_B8 abs. 0x100
2411 2084 2047 634 407 @94
_B7 abs. 0x80
2643 2426 1920 1755 1591 1423 1259 1095 927 774
649 422 @95
_B6 abs. 0x40
2663 2446 1940 1775 1611 1443 1279 1115 947 794
510 442 @96
_B5 abs. 0x20
2683 2491 2466 1795 1631 1463 1299 1135 967 814
@97
_B4 abs. 0x10
2703 2506 2302 1965 1815 1651 1483 1319 1155 987
834 669 531 @98
_B3 abs. 0x8
2723 2526 2323 1980 1835 1671 1503 1339 1175 1007
689 @99
_B2 abs. 0x4
2743 2546 2343 2000 1855 1691 1523 1359 1195 1027
854 709 551 @100
_B1 abs. 0x2
2763 2591 2566 2363 1875 1711 1543 1379 1215 1047
874 729 @101
_B0 abs. 0x1
2783 2606 2383 2134 2109 2067 2025 1895 1731 1563
1399 1235 1067 894 749 571 468 @102
MSK16 abs. 0xffff
2594 2494 2414 2112 2070 2050 637 574 554 534
513 493 471 410 @107
MSK15 abs. 0x7fff
@108
MSK14 abs. 0x3fff
@109
MSK13 abs. 0x1fff
@110
MSK12 abs. 0xfff
@111
MSK11 abs. 0x7ff
@112
MSK10 abs. 0x3ff
@113
MSK9 abs. 0x1ff
@114
MSK8 abs. 0xff
2140 2135 2110 2068 2031 1971 @115
MSK7 abs. 0x7f
@116
MSK6 abs. 0x3f
635 491 @117
MSK5 abs. 0x1f
@118
MSK4 abs. 0xf
469 @119
MSK3 abs. 0x7
2592 2492 2412 2048 @120
MSK2 abs. 0x3
2026 1966 572 552 532 511 408 @121
MSK1 abs. 0x1
@122
DEF macro
2777 2757 2737 2717 2697 2677 2657 2637 2600 2580
2560 2540 2520 2500 2480 2460 2440 2420 2400 2377
2357 2337 2317 2296 2276 2256 2236 2216 2196 2176
2155 2123 2098 2078 2056 2036 2014 1994 1974 1954
1934 1914 1889 1869 1849 1829 1809 1789 1769 1749
1725 1705 1685 1665 1645 1625 1605 1585 1557 1537
1517 1497 1477 1457 1437 1417 1393 1373 1353 1333
1313 1293 1273 1253 1229 1209 1189 1169 1149 1129
1109 1089 1061 1041 1021 1001 981 961 941 921
888 868 848 828 808 788 768 743 723 703
683 663 643 623 603 583 560 540 520 499
479 457 436 416 396 376 356 336 316
SIM$ abs. 0xfffffa00
@310
MCR abs. 0x0
@315
.EXOFF abs. 0xf
@319
_EXOFF abs. 0x8000
@322
.FRZSW abs. 0xe
@339
_FRZSW abs. 0x4000
@342
.FRZBM abs. 0xd
@359
_FRZBM abs. 0x2000
@362
.SLVEN abs. 0xb
@379
_SLVEN abs. 0x800
@382
.SHEN abs. 0x8
@406
SHEN_ abs. 0x100
@407
SHEN_MSK abs. 0x300
410 @408
SHEN_NMSK abs. 0xfcff
@410
.SUPV abs. 0x7
@419
_SUPV abs. 0x80
@422
.MM abs. 0x6
@439
_MM abs. 0x40
@442
.IARB abs. 0x0
@467
IARB_ abs. 0x1
@468
IARB_MSK abs. 0xf
471 @469
IARB_NMSK abs. 0xfff0
@471
SIMTR abs. 0x2
@478
.MASK abs. 0xa
@489
MASK_ abs. 0x400
@490
MASK_MSK abs. 0xfc00
493 @491
MASK_NMSK abs. 0x3ff
@493
.SOSEL abs. 0x6
@509
SOSEL_ abs. 0x40
@510
SOSEL_MSK abs. 0xc0
513 @511
SOSEL_NMSK abs. 0xff3f
@513
.SHIRQ abs. 0x4
@530
SHIRQ_ abs. 0x10
@531
SHIRQ_MSK abs. 0x30
534 @532
SHIRQ_NMSK abs. 0xffcf
@534
.FBIT abs. 0x2
@550
FBIT_ abs. 0x4
@551
FBIT_MSK abs. 0xc
554 @552
FBIT_NMSK abs. 0xfff3
@554
.BWC abs. 0x0
@570
BWC_ abs. 0x1
@571
BWC_MSK abs. 0x3
574 @572
BWC_NMSK abs. 0xfffc
@574
SYNCR abs. 0x4
@581
.WBIT abs. 0xf
@586
_WBIT abs. 0x8000
@589
.XBIT abs. 0xe
@606
_XBIT abs. 0x4000
@609
.Y abs. 0x8
@633
Y_ abs. 0x100
@634
Y_MSK abs. 0x3f00
637 @635
Y_NMSK abs. 0xc0ff
@637
.EDIV abs. 0x7
@646
_EDIV abs. 0x80
@649
.SLIMP abs. 0x4
@666
_SLIMP abs. 0x10
@669
.SLOCK abs. 0x3
@686
_SLOCK abs. 0x8
@689
.RSTEN abs. 0x2
@706
_RSTEN abs. 0x4
@709
.STSIM abs. 0x1
@726
_STSIM abs. 0x2
@729
.STEXT abs. 0x0
@746
_STEXT abs. 0x1
@749
RSR abs. 0x7
@766
.EXT abs. 0x7
@771
_EXT abs. 0x80
@774
.POW abs. 0x6
@791
_POW abs. 0x40
@794
.SW abs. 0x5
@811
_SW abs. 0x20
@814
.HLT abs. 0x4
@831
_HLT abs. 0x10
@834
.LOC abs. 0x2
@851
_LOC abs. 0x4
@854
.SYS abs. 0x1
@871
_SYS abs. 0x2
@874
.TST abs. 0x0
@891
_TST abs. 0x1
@894
SIMTRE abs. 0x8
@909
PORTE abs. 0x11
@920
.PE7 abs. 0x7
@924
_PE7 abs. 0x80
@927
.PE6 abs. 0x6
@944
_PE6 abs. 0x40
@947
.PE5 abs. 0x5
@964
_PE5 abs. 0x20
@967
.PE4 abs. 0x4
@984
_PE4 abs. 0x10
@987
.PE3 abs. 0x3
@1004
_PE3 abs. 0x8
@1007
.PE2 abs. 0x2
@1024
_PE2 abs. 0x4
@1027
.PE1 abs. 0x1
@1044
_PE1 abs. 0x2
@1047
.PE0 abs. 0x0
@1064
_PE0 abs. 0x1
@1067
PORTE1 abs. 0x13
@1084
DDRE abs. 0x15
@1088
.DDE7 abs. 0x7
@1092
_DDE7 abs. 0x80
@1095
.DDE6 abs. 0x6
@1112
_DDE6 abs. 0x40
@1115
.DDE5 abs. 0x5
@1132
_DDE5 abs. 0x20
@1135
.DDE4 abs. 0x4
@1152
_DDE4 abs. 0x10
@1155
.DDE3 abs. 0x3
@1172
_DDE3 abs. 0x8
@1175
.DDE2 abs. 0x2
@1192
_DDE2 abs. 0x4
@1195
.DDE1 abs. 0x1
@1212
_DDE1 abs. 0x2
@1215
.DDE0 abs. 0x0
@1232
_DDE0 abs. 0x1
@1235
PEPAR abs. 0x17
@1252
.PEPA7 abs. 0x7
@1256
_PEPA7 abs. 0x80
@1259
.PEPA6 abs. 0x6
@1276
_PEPA6 abs. 0x40
@1279
.PEPA5 abs. 0x5
@1296
_PEPA5 abs. 0x20
@1299
.PEPA4 abs. 0x4
@1316
_PEPA4 abs. 0x10
@1319
.PEPA3 abs. 0x3
@1336
_PEPA3 abs. 0x8
@1339
.PEPA2 abs. 0x2
@1356
_PEPA2 abs. 0x4
@1359
.PEPA1 abs. 0x1
@1376
_PEPA1 abs. 0x2
@1379
.PEPA0 abs. 0x0
@1396
_PEPA0 abs. 0x1
@1399
PORTF abs. 0x19
@1416
.PF7 abs. 0x7
@1420
_PF7 abs. 0x80
@1423
.PF6 abs. 0x6
@1440
_PF6 abs. 0x40
@1443
.PF5 abs. 0x5
@1460
_PF5 abs. 0x20
@1463
.PF4 abs. 0x4
@1480
_PF4 abs. 0x10
@1483
.PF3 abs. 0x3
@1500
_PF3 abs. 0x8
@1503
.PF2 abs. 0x2
@1520
_PF2 abs. 0x4
@1523
.PF1 abs. 0x1
@1540
_PF1 abs. 0x2
@1543
.PF0 abs. 0x0
@1560
_PF0 abs. 0x1
@1563
PORTF1 abs. 0x1b
@1580
DDRF abs. 0x1d
@1584
.DDF7 abs. 0x7
@1588
_DDF7 abs. 0x80
@1591
.DDF6 abs. 0x6
@1608
_DDF6 abs. 0x40
@1611
.DDF5 abs. 0x5
@1628
_DDF5 abs. 0x20
@1631
.DDF4 abs. 0x4
@1648
_DDF4 abs. 0x10
@1651
.DDF3 abs. 0x3
@1668
_DDF3 abs. 0x8
@1671
.DDF2 abs. 0x2
@1688
_DDF2 abs. 0x4
@1691
.DDF1 abs. 0x1
@1708
_DDF1 abs. 0x2
@1711
.DDF0 abs. 0x0
@1728
_DDF0 abs. 0x1
@1731
PFPAR abs. 0x1f
@1748
.PFPA7 abs. 0x7
@1752
_PFPA7 abs. 0x80
@1755
.PFPA6 abs. 0x6
@1772
_PFPA6 abs. 0x40
@1775
.PFPA5 abs. 0x5
@1792
_PFPA5 abs. 0x20
@1795
.PFPA4 abs. 0x4
@1812
_PFPA4 abs. 0x10
@1815
.PFPA3 abs. 0x3
@1832
_PFPA3 abs. 0x8
@1835
.PFPA2 abs. 0x2
@1852
_PFPA2 abs. 0x4
@1855
.PFPA1 abs. 0x1
@1872
_PFPA1 abs. 0x2
@1875
.PFPA0 abs. 0x0
@1892
_PFPA0 abs. 0x1
@1895
SYPCR abs. 0x21
@1912
.SWE abs. 0x7
@1917
_SWE abs. 0x80
@1920
.SWP abs. 0x6
@1937
_SWP abs. 0x40
@1940
.SWT abs. 0x4
@1964
SWT_ abs. 0x10
@1965
SWT_MSK abs. 0x30
1971 @1966
SWT_NMSK abs. 0xcf
@1971
.HME abs. 0x3
@1977
_HME abs. 0x8
@1980
.BME abs. 0x2
@1997
_BME abs. 0x4
@2000
.BMT abs. 0x0
@2024
BMT_ abs. 0x1
@2025
BMT_MSK abs. 0x3
2031 @2026
BMT_NMSK abs. 0xfc
@2031
PICR abs. 0x22
@2035
.PIRQL abs. 0x8
@2046
PIRQL_ abs. 0x100
@2047
PIRQL_MSK abs. 0x700
2050 @2048
PIRQL_NMSK abs. 0xf8ff
@2050
.PIV abs. 0x0
@2066
PIV_ abs. 0x1
@2067
PIV_MSK abs. 0xff
2070 @2068
PIV_NMSK abs. 0xff00
@2070
PITR abs. 0x24
@2077
.PTP abs. 0x8
@2081
_PTP abs. 0x100
@2084
.PITM abs. 0x0
@2108
PITM_ abs. 0x1
@2109
PITM_MSK abs. 0xff
2112 @2110
PITM_NMSK abs. 0xff00
@2112
SWSR abs. 0x27
@2121
.SWSR abs. 0x0
@2133
SWSR_ abs. 0x1
@2134
SWSR_MSK abs. 0xff
2140 @2135
SWSR_NMSK abs. 0x0
@2140
TSTMSRA abs. 0x30
@2146
TSTMSRB abs. 0x32
@2148
TSTSC abs. 0x34
@2150
TSTRC abs. 0x36
@2152
CREG abs. 0x38
@2154
.BUSY abs. 0xf
@2158
_BUSY abs. 0x8000
@2161
.TMARM abs. 0xe
@2179
_TMARM abs. 0x4000
@2182
.COMP abs. 0xd
@2199
_COMP abs. 0x2000
@2202
.IMBTST abs. 0xc
@2219
_IMBTST abs. 0x1000
@2222
.CPUTR abs. 0xb
@2239
_CPUTR abs. 0x800
@2242
.QBIT abs. 0xa
@2259
_QBIT abs. 0x400
@2262
.MUXEL abs. 0x9
@2279
_MUXEL abs. 0x200
@2282
.ACUT abs. 0x4
@2299
_ACUT abs. 0x10
@2302
.SCONT abs. 0x3
@2320
_SCONT abs. 0x8
@2323
.SSHOP abs. 0x2
@2340
_SSHOP abs. 0x4
@2343
.SATO abs. 0x1
@2360
_SATO abs. 0x2
@2363
.ETM abs. 0x0
@2380
_ETM abs. 0x1
@2383
DREG abs. 0x3a
@2399
.WAIT abs. 0x8
@2410
WAIT_ abs. 0x100
@2411
WAIT_MSK abs. 0x700
2414 @2412
WAIT_NMSK abs. 0xf8ff
@2414
.MSRA18 abs. 0x7
@2423
_MSRA18 abs. 0x80
@2426
.MSRA17 abs. 0x6
@2443
_MSRA17 abs. 0x40
@2446
.MSRA16 abs. 0x5
@2463
_MSRA16 abs. 0x20
@2466
.MSRA abs. 0x5
@2490
MSRA_ abs. 0x20
@2491
MSRA_MSK abs. 0xe0
2494 @2492
MSRA_NMSK abs. 0xff1f
@2494
.MSRAC abs. 0x4
@2503
_MSRAC abs. 0x10
@2506
.MSRB18 abs. 0x3
@2523
_MSRB18 abs. 0x8
@2526
.MSRB17 abs. 0x2
@2543
_MSRB17 abs. 0x4
@2546
.MSRB16 abs. 0x1
@2563
_MSRB16 abs. 0x2
@2566
.MSRB abs. 0x1
@2590
MSRB_ abs. 0x2
@2591
MSRB_MSK abs. 0xe
2594 @2592
MSRB_NMSK abs. 0xfff1
@2594
.MSRBC abs. 0x0
@2603
_MSRBC abs. 0x1
@2606
WAIT$2 abs. 0x0
@2621
WAIT$4 abs. 0x1
@2622
WAIT$6 abs. 0x2
@2623
WAIT$8 abs. 0x3
@2624
WAIT$10 abs. 0x4
@2625
WAIT$12 abs. 0x5
@2626
WAIT$14 abs. 0x6
@2627
WAIT$16 abs. 0x7
@2628
PORTC abs. 0x41
@2636
.PC7 abs. 0x7
@2640
_PC7 abs. 0x80
@2643
.PC6 abs. 0x6
@2660
_PC6 abs. 0x40
@2663
.PC5 abs. 0x5
@2680
_PC5 abs. 0x20
@2683
.PC4 abs. 0x4
@2700
_PC4 abs. 0x10
@2703
.PC3 abs. 0x3
@2720
_PC3 abs. 0x8
@2723
.PC2 abs. 0x2
@2740
_PC2 abs. 0x4
@2743
.PC1 abs. 0x1
@2760
_PC1 abs. 0x2
@2763
.PC0 abs. 0x0
@2780
_PC0 abs. 0x1
@2783
CSPAR0 abs. 0x44
@2800
CSPAR1 abs. 0x46
@2802
CSBARBT abs. 0x48
@2804
CSORBT abs. 0x4a
@2810
CSBAR0 abs. 0x4c
@2822
CSOR0 abs. 0x4e
@2824
CSBAR1 abs. 0x50
@2826
CSOR1 abs. 0x52
@2828
CSBAR2 abs. 0x54
@2830
CSOR2 abs. 0x56
@2832
CSBAR3 abs. 0x58
@2834
CSOR3 abs. 0x5a
@2836
CSBAR4 abs. 0x5c
@2838
CSOR4 abs. 0x5e
@2840
CSBAR5 abs. 0x60
@2842
CSOR5 abs. 0x62
@2844
CSBAR6 abs. 0x64
@2846
CSOR6 abs. 0x66
@2848
CSBAR7 abs. 0x68
@2850
CSOR7 abs. 0x6a
@2852
CSBAR8 abs. 0x6c
@2854
CSOR8 abs. 0x6e
@2856
CSBAR9 abs. 0x70
@2858
CSOR9 abs. 0x72
@2860
CSBAR10 abs. 0x74
@2862
CSOR10 abs. 0x76
@2864
CSBAR_XX abs. 0x0
@2878
CSOR_XX abs. 0x0
@2879
B2K abs. 0x0
@2881
B8K abs. 0x1
@2882
B16K abs. 0x2
@2883
B64K abs. 0x3
@2884
B128K abs. 0x4
@2885
B256K abs. 0x5
@2886
B512K abs. 0x6
@2887
B1M abs. 0x7
@2888
ASYNC abs. 0x0
@2889
SYNC abs. 0x8000
@2890
CS_UPPB abs. 0x4000
@2891
CS_LOWB abs. 0x2000
@2892
CS_BOTHB abs. 0x6000
@2893
CS_R abs. 0x800
@2894
CS_W abs. 0x1000
@2895
CS_RW abs. 0x1800
@2896
CS_AS abs. 0x0
@2897
CS_DS abs. 0x400
@2898
CS_FAST abs. 0xe
@2899
CS_EXT abs. 0xf
@2900
CS_WAIT abs. 0x40
@2901
CS_CSP abs. 0x0
@2902
CS_USP abs. 0x10
@2903
CS_SSP abs. 0x20
@2904
CS_SUSP abs. 0x30
@2905
CS_LVL abs. 0x2
@2906
CS_AVEC abs. 0x1
@2907
414 symbols
